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import simple_sume_switch from switch_calc

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Nico Schottelius 4 years ago
parent 706eac0e41
commit 0645646df5
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60
netpfga/minip4/simple_sume_switch/Makefile
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#
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# File:
# Makefile
#
# Project:
# reference projects
#
#
# Description:
# This makefile is used to generate and compile SDK project for NetFPGA reference projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
HW = hw
SW = sw/embedded/
TEST = test
all: clean
make -C ${HW} project
make -C ${HW} export_to_sdk
make -C ${SW} project
make -C ${SW} compile
make -C ${HW} load_elf
clean:
make -C ${HW} distclean
make -C ${SW} distclean
rm -rfv vivado*;\

34
netpfga/minip4/simple_sume_switch/bitfiles/README
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#
# Copyright (c) 2017 Stephen Ibanez
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
This version allows the control plane to access all entries in the const
register

36
netpfga/minip4/simple_sume_switch/bitfiles/program_switch.sh
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#!/bin/bash
#
# Copyright (c) 2017 Stephen Ibanez
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Program the switch with the bit file and then configure the tables
${SUME_SDNET}/tools/program_switch.sh switch_calc.bit config_writes.sh

173
netpfga/minip4/simple_sume_switch/hw/Makefile
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#
# Copyright (c) 2015 Noa Zilberman, Georgina Kalogeridou
# All rights reserved.
#
# File:
# Makefile
#
# Description:
# This makefile is used to generate and compile hw projects
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
PROJ = ${NF_PROJECT_NAME}
all:
@echo ""
@echo "NetFPGA-SUME Referece Project HW Makefile"
@echo ""
@echo "make TARGETS"
@echo "------------------------------------------------------"
@echo "project: Create hardware project"
@echo "sim: Run project simulation"
@echo "export_to_sdk: Export implemented project to sw/embedded"
@echo "load_elf: Load ELF file for specified project"
@echo ""
@echo "clean: Remove specified project"
@echo "distclean: Remove all generated projects"
@echo ""
.PHONY: clean project export_to_sdk load_elf
project: identifier
echo "Create reference project under folder /project";\
if test -d project/; then\
echo "Project already exists"; \
else \
vivado -mode batch -source tcl/${PROJ}.tcl;\
if [ -f patch/${PROJ}.patch ]; then\
patch -p1 < patch/${PROJ}.patch;\
fi;\
fi;\
projectgui:
echo "Create reference project under folder /project";\
if test -d project/; then\
echo "Project already exists"; \
else \
vivado -mode gui -source tcl/${PROJ}.tcl;\
if [ -f patch/${PROJ}.patch ]; then\
patch -p1 < patch/${PROJ}.patch;\
fi;\
fi;\
export_to_sdk: identifier
if test -d project; then\
echo "export ${PROJ} project to SDK"; \
vivado -mode tcl -source tcl/export_hardware.tcl -tclargs ${PROJ};\
else \
echo "Project ${PROJ} does not exist.";\
echo "Please run \"make project\" to create and build the project first";\
fi;\
load_elf:
@if [ ! -d ../bitfiles ]; then mkdir ../bitfiles; fi;
if test -d project; then\
echo "export ${PROJ} project to SDK"; \
vivado -mode tcl -source tcl/load_elf.tcl -tclargs ${PROJ};\
else \
echo "Project ${PROJ} does not exist.";\
echo "Please run \"make project\" to create and build the project first";\
fi;\
identifier:
rm -f ../hw/create_ip/id_rom16x32.coe
cp ${SUME_FOLDER}/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
echo 16028002 >> rom_data.txt
echo `${SUME_FOLDER}/run_tag.sh` >> rom_data.txt
echo 00000204 >> rom_data.txt
echo 0000FFFF >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
cp ${SUME_FOLDER}/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
mv -f id_rom16x32.coe ../hw/create_ip/
mv -f rom_data.txt ../hw/create_ip/
sim: simclean identifier
cp -f $(NF_DESIGN_DIR)/test/reg_defines_${NF_PROJECT_NAME}.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_${NF_PROJECT_NAME}.py
vivado -mode batch -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
reg:
vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/${NF_PROJECT_NAME}_defines.tcl
vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/export_registers.tcl
cd ../sw/embedded/src && cp ${SUME_FOLDER}/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../
cd ../sw/embedded && cp ${SUME_FOLDER}/tools/scripts/python_parser.py . && python python_parser.py
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_${NF_PROJECT_NAME}.py
simgui: simclean identifier
cp -f $(NF_DESIGN_DIR)/test/reg_defines_simple_sume_switch.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_simple_sume_switch.py
vivado -mode gui -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
simclean:
rm -rf proj_* vivado*.* *.*~ .Xil* $(NF_DESIGN_DIR)/hw/ip_repo/ $(NF_DESIGN_DIR)/hw/project/
rm -rf *[0-9]_{stim,expected,log}.axi
rm -f *.axi
rm -f portconfig.sim
rm -f seed
rm -f *.log
rm -f ../test/Makefile
rm -rf ../test/*.log
rm -rf ../test/*.axi
rm -rf ../test/seed
rm -rf ../test/*.sim
rm -rf ../test/proj_*
rm -rf ../test/ip_repo
rm -f ../test/vivado*.*
rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.py
rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.pyc
distclean: clean
clean: simclean
rm -rfv project;\
rm -rfv ../sw/embedded/project;\
rm -rfv vivado*;\
rm -rfv *.log;\
rm -rfv .Xil;\
rm -rfv ..rej;\
rm -rfv .srcs;\
rm -rfv webtalk*;\
rm -rfv *.*~;\
rm -rfv ip_repo;\
rm -rfv ip_proj;\
rm -rfv std;\

156
netpfga/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc
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#
# Copyright (c) 2015 Noa Zilberman, Yury Audzevich
# All rights reserved.
#
# File:
# nf_sume_10g.xdc
#
# Author: Noa Zilberman
#
# Description:
# Location constraints for 4x 10GbE SFP+ interface used in reference
# projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# XGE-SFP0 -- SUME -- THE FIRST INTERFACE FROM THE TOP OF THE BOARD
set_property PACKAGE_PIN M18 [get_ports sfp0_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_disable]
set_property PACKAGE_PIN M19 [get_ports sfp0_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_fault]
set_property PACKAGE_PIN N18 [get_ports sfp0_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y39 [get_cells -hier -filter name=~*interface_0*gthe2_i]
# XGE-SFP1 -- SUME
set_property PACKAGE_PIN B31 [get_ports sfp1_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_disable]
set_property PACKAGE_PIN C26 [get_ports sfp1_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_fault]
set_property PACKAGE_PIN L19 [get_ports sfp1_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y38 [get_cells -hier -filter name=~*interface_1*gthe2_i]
#set_property LOC GTHE2_CHANNEL_X1Y38 [get_cells nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/ten_gig_eth_pcs_pma/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i]
# XGE-SFP2 -- SUME
set_property PACKAGE_PIN J38 [get_ports sfp2_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_disable]
set_property PACKAGE_PIN E39 [get_ports sfp2_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_fault]
set_property PACKAGE_PIN J37 [get_ports sfp2_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y37 [get_cells -hier -filter name=~*interface_2*gthe2_i]
# XGE-SFP3 -- SUME -- FIRST FROM THE BOTTOM (to PCIe)
set_property PACKAGE_PIN L21 [get_ports sfp3_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_disable]
set_property PACKAGE_PIN J26 [get_ports sfp3_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_fault]
set_property PACKAGE_PIN H36 [get_ports sfp3_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y36 [get_cells -hier -filter name=~*interface_3*gthe2_i]
#set_property LOC GTHE2_CHANNEL_X1Y36 [get_cells nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/ten_gig_eth_pcs_pma/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i]
## -- SFP clocks
## -- The clock is supplied by Si5324 chip;
## -- the clock is configured through microblaze.
set_property PACKAGE_PIN E10 [get_ports xphy_refclk_p]
set_property PACKAGE_PIN E9 [get_ports xphy_refclk_n]
create_clock -period 6.400 [get_ports xphy_refclk_p]
#create_clock -period 6.400 -name xgemac_clk_156 [get_ports xphy_refclk_p]
# XGE TX/RX LEDs
# GRN - TX
# YLW - RX
set_property PACKAGE_PIN G13 [get_ports sfp0_tx_led]
set_property PACKAGE_PIN AL22 [get_ports sfp1_tx_led]
set_property PACKAGE_PIN AY18 [get_ports sfp2_tx_led]
set_property PACKAGE_PIN P31 [get_ports sfp3_tx_led]
set_property PACKAGE_PIN L15 [get_ports sfp0_rx_led]
set_property PACKAGE_PIN BA20 [get_ports sfp1_rx_led]
set_property PACKAGE_PIN AY17 [get_ports sfp2_rx_led]
set_property PACKAGE_PIN K32 [get_ports sfp3_rx_led]
set_property IOSTANDARD LVCMOS15 [get_ports sfp?_?x_led]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets nf_10g_shared_i/inst/refclk]
## Timing Constraints
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_0*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_0*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_1*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_1*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_2*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_2*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_3*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_3*gthe2_i/TXOUTCLK]
## Timing Constraints
###################
## Other constraints
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks clk_250mhz_mux_x0y1] -to [get_clocks clk_125mhz_x0y1]
set_false_path -from [get_clocks clk_125mhz_x0y1] -to [get_clocks clk_250mhz_mux_x0y1]
set_false_path -from [get_clocks userclk1] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks axi_clk]
set_false_path -from [get_clocks axi_clk] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks userclk1]
set_false_path -from [get_clocks -filter name=~*interface_*gthe2_i/RXOUTCLK] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks -filter name=~*interface_*gthe2_i/RXOUTCLK]
set_false_path -from [get_clocks -filter name=~*interface_*gthe2_i/TXOUTCLK] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks -filter name=~*interface_*gthe2_i/TXOUTCLK]

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netpfga/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc
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# Copyright (c) 2015 Tinghui Wang
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# File:
# nf_sume_general.xdc
#
# Author:
# Tinghui Wang (Steve)
# Modified by:
# Noa Zilberman
#
# Description:
# System general constraints for NetFPGA-SUME board.
# The file includes constraints for:
# - Master FPGA 200MHz clock (fpga_sysclk)
# - Main I2C Bus (iic_fpga, si5324_rst_n)
# - UART (115200-8N1)
# - Btn0 is used as system sys_reset_n (active high)
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
## -- The following two properties should be set for every design
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
## -- PCIe Transceiver clock (100 MHz)
set_property LOC IBUFDS_GTE2_X1Y11 [get_cells IBUFDS_GTE2_inst]
create_clock -period 10.000 -name sys_clk -add [get_pins -hier -filter name=~*IBUFDS_GTE2_inst/O]
create_clock -period 10.000 -name sys_clkp -waveform {0.000 5.000} [get_ports sys_clkp]
## -- PCIe sys reset
set_property PACKAGE_PIN AY35 [get_ports sys_reset_n]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset_n]
set_property PULLUP true [get_ports sys_reset_n]
set_false_path -from [get_ports sys_reset_n]
# 200MHz System Clock -- SUME
set_property PACKAGE_PIN H19 [get_ports fpga_sysclk_p]
set_property VCCAUX_IO DONTCARE [get_ports fpga_sysclk_p]
set_property IOSTANDARD LVDS [get_ports fpga_sysclk_p]
set_property IOSTANDARD LVDS [get_ports fpga_sysclk_n]
#create_clock -period 5.00 [get_ports {axi_clocking_i/s_axi_aclk}]
create_clock -period 5.000 -name fpga_sysclk_p -waveform {0.000 2.500} [get_ports fpga_sysclk_p]
## -- 200MHz & 100MHz clks
create_clock -period 5.000 -name clk_200 -add [get_pins -hier -filter name=~*axi_clocking_i*clk_wiz_i/clk_out1]
create_clock -period 10.000 -name axi_clk -add [get_pins -hier -filter name=~*axi_lite_bufg0/O]
# Main I2C Bus - 100KHz - SUME
set_property IOSTANDARD LVCMOS18 [get_ports i2c_clk]
set_property SLEW SLOW [get_ports i2c_clk]
set_property DRIVE 16 [get_ports i2c_clk]
set_property PULLUP true [get_ports i2c_clk]
set_property PACKAGE_PIN AK24 [get_ports i2c_clk]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_data]
set_property SLEW SLOW [get_ports i2c_data]
set_property DRIVE 16 [get_ports i2c_data]
set_property PULLUP true [get_ports i2c_data]
set_property PACKAGE_PIN AK25 [get_ports i2c_data]
# i2c_reset[0] - i2c_mux reset - high active
# i2c_reset[1] - si5324 reset - high active
set_property SLEW SLOW [get_ports {i2c_reset[*]}]
set_property DRIVE 16 [get_ports {i2c_reset[*]}]
set_property PACKAGE_PIN AM39 [get_ports {i2c_reset[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {i2c_reset[0]}]
set_property PACKAGE_PIN BA29 [get_ports {i2c_reset[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {i2c_reset[1]}]
## -- USER LEDS
set_property PACKAGE_PIN AR22 [get_ports {leds[0]}]
set_property PACKAGE_PIN AR23 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[1]}]
set_false_path -to [get_ports -filter NAME=~led*]
# UART - 115200 8-1 no parity
set_property PACKAGE_PIN AY19 [get_ports uart_rxd]
set_property PACKAGE_PIN BA19 [get_ports uart_txd]
set_property IOSTANDARD LVCMOS15 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS15 [get_ports uart_txd]
#False paths
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out}]
# Bitfile Generation
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_false_path -from [get_clocks sys_clk] -to [get_clocks clk_200]
set_false_path -from [get_clocks axi_clk] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks axi_clk]

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netpfga/minip4/simple_sume_switch/hw/create_ip/nf_10ge_interface.tcl
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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
# Set variables
# CORE CONFIG parameters
set sharedLogic "FALSE"
set tdataWidth 256
set convWidth [expr $tdataWidth/8]
if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
set supportLevel 1
} else {
set supportLevel 0
}
create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
reset_target all [get_ips axi_10g_ethernet_nonshared]
generate_target all [get_ips axi_10g_ethernet_nonshared]
create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
reset_target all [get_ips fifo_generator_status]
generate_target all [get_ips fifo_generator_status]
create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
set_property generate_synth_checkpoint false [get_files inverter_0.xci]
reset_target all [get_ips inverter_0]
generate_target all [get_ips inverter_0]
create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
reset_target all [get_ips fifo_generator_1_9]
generate_target all [get_ips fifo_generator_1_9]

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netpfga/minip4/simple_sume_switch/hw/create_ip/nf_10ge_interface_shared.tcl
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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
# Set variables.
## CORE CONFIGURATION parameters
# should correspond to hdl params
set sharedLogic "TRUE"
set tdataWidth 256
set convWidth [expr $tdataWidth/8]
if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
set supportLevel 1
} else {
set supportLevel 0
}
create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared
set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared]
set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci]
reset_target all [get_ips axi_10g_ethernet_shared]
generate_target all [get_ips axi_10g_ethernet_shared]

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netpfga/minip4/simple_sume_switch/hw/create_ip/nf_sume_sdnet.tcl.bak
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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 1.1 -module_name axis_data_fifo_0
set_property -dict [list CONFIG.TDATA_NUM_BYTES {32} CONFIG.TUSER_WIDTH {160} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1}] [get_ips axis_data_fifo_0]
set_property generate_synth_checkpoint false [get_files axis_data_fifo_0.xci]
reset_target all [get_ips axis_data_fifo_0]
generate_target all [get_ips axis_data_fifo_0]

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netpfga/minip4/simple_sume_switch/hw/hdl/axi_clocking.v
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//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// axi_clocking.v
//
// Module:
// axi_clocking
//
// Author: Noa Zilberman
//
// Description:
// Sharable clocking resources for NetFPGA SUME
//
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
`timescale 1ps / 1ps
(* dont_touch = "yes" *)
module axi_clocking
(
// Inputs
input clk_in_p,
input clk_in_n,
input resetn,
// Status outputs
// IBUFDS 200MHz
output locked,
output clk_200
);
// Signal declarations
wire s_axi_dcm_aclk0;
wire clkfbout;
// 200MHz differencial into single-rail
IBUFDS clkin1_buf
(.O (clkin1),
.I (clk_in_p),
.IB (clk_in_n)
);
clk_wiz_ip clk_wiz_i
(
// Clock in ports
.clk_in1(clkin1), // input clk_in1
// Clock out ports
.clk_out1(clk_200), // output clk_out1
// Status and control signals
.resetn(resetn), // input resetn
.locked(locked));
endmodule

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netpfga/minip4/simple_sume_switch/hw/hdl/nf_datapath.v
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`timescale 1ns / 1ps
//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// nf_datapath.v
//
// Module:
// nf_datapath
//
// Author: Noa Zilberman
//
// Description:
// NetFPGA user data path wrapper, wrapping input arbiter, output port lookup and output queues
//
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
module nf_datapath #(
//Slave AXI parameters
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_BASEADDR = 32'h00000000,
// Master AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter NUM_QUEUES=5,
parameter DIGEST_WIDTH =80
)
(
//Datapath clock
input axis_aclk,
input axis_resetn,
//Registers clock
input axi_aclk,
input axi_resetn,
// Slave AXI Ports
input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_AWADDR,
input S0_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S0_AXI_WSTRB,
input S0_AXI_WVALID,
input S0_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_ARADDR,
input S0_AXI_ARVALID,
input S0_AXI_RREADY,
output S0_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_RDATA,
output [1 : 0] S0_AXI_RRESP,
output S0_AXI_RVALID,
output S0_AXI_WREADY,
output [1 :0] S0_AXI_BRESP,
output S0_AXI_BVALID,
output S0_AXI_AWREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_AWADDR,
input S1_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S1_AXI_WSTRB,
input S1_AXI_WVALID,
input S1_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_ARADDR,
input S1_AXI_ARVALID,
input S1_AXI_RREADY,
output S1_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_RDATA,
output [1 : 0] S1_AXI_RRESP,
output S1_AXI_RVALID,
output S1_AXI_WREADY,
output [1 :0] S1_AXI_BRESP,
output S1_AXI_BVALID,
output S1_AXI_AWREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_AWADDR,
input S2_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S2_AXI_WSTRB,
input S2_AXI_WVALID,
input S2_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_ARADDR,
input S2_AXI_ARVALID,
input S2_AXI_RREADY,
output S2_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_RDATA,
output [1 : 0] S2_AXI_RRESP,
output S2_AXI_RVALID,
output S2_AXI_WREADY,
output [1 :0] S2_AXI_BRESP,
output S2_AXI_BVALID,
output S2_AXI_AWREADY,
// Slave Stream Ports (interface from Rx queues)
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_0_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_0_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_0_tuser,
input s_axis_0_tvalid,
output s_axis_0_tready,
input s_axis_0_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_1_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_1_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_1_tuser,
input s_axis_1_tvalid,
output s_axis_1_tready,
input s_axis_1_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_2_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_2_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_2_tuser,
input s_axis_2_tvalid,
output s_axis_2_tready,
input s_axis_2_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_3_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_3_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_3_tuser,
input s_axis_3_tvalid,
output s_axis_3_tready,
input s_axis_3_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_4_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_4_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_4_tuser,
input s_axis_4_tvalid,
output s_axis_4_tready,
input s_axis_4_tlast,
// Master Stream Ports (interface to TX queues)
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_0_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_0_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_0_tuser,
output m_axis_0_tvalid,
input m_axis_0_tready,
output m_axis_0_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_1_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_1_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_1_tuser,
output m_axis_1_tvalid,
input m_axis_1_tready,
output m_axis_1_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_2_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_2_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_2_tuser,
output m_axis_2_tvalid,
input m_axis_2_tready,
output m_axis_2_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_3_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_3_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_3_tuser,
output m_axis_3_tvalid,
input m_axis_3_tready,
output m_axis_3_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_4_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_4_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_4_tuser,
output m_axis_4_tvalid,
input m_axis_4_tready,
output m_axis_4_tlast
);
localparam C_AXIS_TUSER_DIGEST_WIDTH = 304;
//internal connectivity
(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_opl_tdata;
(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_opl_tkeep;
(* mark_debug = "true" *) wire [C_AXIS_TUSER_DIGEST_WIDTH-1:0] m_axis_opl_tuser;
(* mark_debug = "true" *) wire m_axis_opl_tvalid;
(* mark_debug = "true" *) wire m_axis_opl_tready;
(* mark_debug = "true" *) wire m_axis_opl_tlast;
(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] s_axis_opl_tdata;
(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_opl_tkeep;
(* mark_debug = "true" *) wire [C_M_AXIS_TUSER_WIDTH-1:0] s_axis_opl_tuser;
(* mark_debug = "true" *) wire s_axis_opl_tvalid;
(* mark_debug = "true" *) wire s_axis_opl_tready;
(* mark_debug = "true" *) wire s_axis_opl_tlast;
localparam Q_SIZE_WIDTH = 16;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf0_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf1_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf2_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf3_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] dma_q_size;
//Input Arbiter
input_arbiter_ip
input_arbiter_v1_0 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.m_axis_tdata (s_axis_opl_tdata),
.m_axis_tkeep (s_axis_opl_tkeep),
.m_axis_tuser (s_axis_opl_tuser),
.m_axis_tvalid(s_axis_opl_tvalid),
.m_axis_tready(s_axis_opl_tready),
.m_axis_tlast (s_axis_opl_tlast),
.s_axis_0_tdata (s_axis_0_tdata),
.s_axis_0_tkeep (s_axis_0_tkeep),
.s_axis_0_tuser (s_axis_0_tuser),
.s_axis_0_tvalid(s_axis_0_tvalid),
.s_axis_0_tready(s_axis_0_tready),
.s_axis_0_tlast (s_axis_0_tlast),
.s_axis_1_tdata (s_axis_1_tdata),
.s_axis_1_tkeep (s_axis_1_tkeep),
.s_axis_1_tuser (s_axis_1_tuser),
.s_axis_1_tvalid(s_axis_1_tvalid),
.s_axis_1_tready(s_axis_1_tready),
.s_axis_1_tlast (s_axis_1_tlast),
.s_axis_2_tdata (s_axis_2_tdata),
.s_axis_2_tkeep (s_axis_2_tkeep),
.s_axis_2_tuser (s_axis_2_tuser),
.s_axis_2_tvalid(s_axis_2_tvalid),
.s_axis_2_tready(s_axis_2_tready),
.s_axis_2_tlast (s_axis_2_tlast),
.s_axis_3_tdata (s_axis_3_tdata),
.s_axis_3_tkeep (s_axis_3_tkeep),
.s_axis_3_tuser (s_axis_3_tuser),
.s_axis_3_tvalid(s_axis_3_tvalid),
.s_axis_3_tready(s_axis_3_tready),
.s_axis_3_tlast (s_axis_3_tlast),
.s_axis_4_tdata (s_axis_4_tdata),
.s_axis_4_tkeep (s_axis_4_tkeep),
.s_axis_4_tuser (s_axis_4_tuser),
.s_axis_4_tvalid(s_axis_4_tvalid),
.s_axis_4_tready(s_axis_4_tready),
.s_axis_4_tlast (s_axis_4_tlast),
.S_AXI_AWADDR(S0_AXI_AWADDR),
.S_AXI_AWVALID(S0_AXI_AWVALID),
.S_AXI_WDATA(S0_AXI_WDATA),
.S_AXI_WSTRB(S0_AXI_WSTRB),
.S_AXI_WVALID(S0_AXI_WVALID),
.S_AXI_BREADY(S0_AXI_BREADY),
.S_AXI_ARADDR(S0_AXI_ARADDR),
.S_AXI_ARVALID(S0_AXI_ARVALID),
.S_AXI_RREADY(S0_AXI_RREADY),
.S_AXI_ARREADY(S0_AXI_ARREADY),
.S_AXI_RDATA(S0_AXI_RDATA),
.S_AXI_RRESP(S0_AXI_RRESP),
.S_AXI_RVALID(S0_AXI_RVALID),
.S_AXI_WREADY(S0_AXI_WREADY),
.S_AXI_BRESP(S0_AXI_BRESP),
.S_AXI_BVALID(S0_AXI_BVALID),
.S_AXI_AWREADY(S0_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn),
.pkt_fwd()
);
// SUME SDNet Module
nf_sume_sdnet_ip
nf_sume_sdnet_wrapper_1 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.m_axis_tdata (m_axis_opl_tdata),
.m_axis_tkeep (m_axis_opl_tkeep),
.m_axis_tuser (m_axis_opl_tuser),
.m_axis_tvalid(m_axis_opl_tvalid),
.m_axis_tready(m_axis_opl_tready),
.m_axis_tlast (m_axis_opl_tlast),
.s_axis_tdata (s_axis_opl_tdata),
.s_axis_tkeep (s_axis_opl_tkeep),
.s_axis_tuser ({dma_q_size, nf3_q_size, nf2_q_size, nf1_q_size, nf0_q_size, s_axis_opl_tuser[C_M_AXIS_TUSER_WIDTH-DIGEST_WIDTH-1:0]}),
.s_axis_tvalid(s_axis_opl_tvalid),
.s_axis_tready(s_axis_opl_tready),
.s_axis_tlast (s_axis_opl_tlast),
.S_AXI_AWADDR(S1_AXI_AWADDR),
.S_AXI_AWVALID(S1_AXI_AWVALID),
.S_AXI_WDATA(S1_AXI_WDATA),
.S_AXI_WSTRB(S1_AXI_WSTRB),
.S_AXI_WVALID(S1_AXI_WVALID),
.S_AXI_BREADY(S1_AXI_BREADY),
.S_AXI_ARADDR(S1_AXI_ARADDR),
.S_AXI_ARVALID(S1_AXI_ARVALID),
.S_AXI_RREADY(S1_AXI_RREADY),
.S_AXI_ARREADY(S1_AXI_ARREADY),
.S_AXI_RDATA(S1_AXI_RDATA),
.S_AXI_RRESP(S1_AXI_RRESP),
.S_AXI_RVALID(S1_AXI_RVALID),
.S_AXI_WREADY(S1_AXI_WREADY),
.S_AXI_BRESP(S1_AXI_BRESP),
.S_AXI_BVALID(S1_AXI_BVALID),
.S_AXI_AWREADY(S1_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn)
);
(* mark_debug = "true" *) wire [C_S_AXI_DATA_WIDTH-1:0] bytes_dropped;
(* mark_debug = "true" *) wire [5-1:0] pkt_dropped;
// assign nf0_q_size = 'd12;
// assign nf1_q_size = 'd13;
// assign nf2_q_size = 'd14;
// assign nf3_q_size = 'd15;
// assign dma_q_size = 'd16;
//Output queues
sss_output_queues_ip
bram_output_queues_1 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.s_axis_tdata (m_axis_opl_tdata),
.s_axis_tkeep (m_axis_opl_tkeep),
.s_axis_tuser (m_axis_opl_tuser),
.s_axis_tvalid (m_axis_opl_tvalid),
.s_axis_tready (m_axis_opl_tready),
.s_axis_tlast (m_axis_opl_tlast),
.m_axis_0_tdata (m_axis_0_tdata),
.m_axis_0_tkeep (m_axis_0_tkeep),
.m_axis_0_tuser (m_axis_0_tuser),
.m_axis_0_tvalid(m_axis_0_tvalid),
.m_axis_0_tready(m_axis_0_tready),
.m_axis_0_tlast (m_axis_0_tlast),
.m_axis_1_tdata (m_axis_1_tdata),
.m_axis_1_tkeep (m_axis_1_tkeep),
.m_axis_1_tuser (m_axis_1_tuser),
.m_axis_1_tvalid(m_axis_1_tvalid),
.m_axis_1_tready(m_axis_1_tready),
.m_axis_1_tlast (m_axis_1_tlast),
.m_axis_2_tdata (m_axis_2_tdata),
.m_axis_2_tkeep (m_axis_2_tkeep),
.m_axis_2_tuser (m_axis_2_tuser),
.m_axis_2_tvalid(m_axis_2_tvalid),
.m_axis_2_tready(m_axis_2_tready),
.m_axis_2_tlast (m_axis_2_tlast),
.m_axis_3_tdata (m_axis_3_tdata),
.m_axis_3_tkeep (m_axis_3_tkeep),
.m_axis_3_tuser (m_axis_3_tuser),
.m_axis_3_tvalid(m_axis_3_tvalid),
.m_axis_3_tready(m_axis_3_tready),
.m_axis_3_tlast (m_axis_3_tlast),
.m_axis_4_tdata (m_axis_4_tdata),
.m_axis_4_tkeep (m_axis_4_tkeep),
.m_axis_4_tuser (m_axis_4_tuser),
.m_axis_4_tvalid(m_axis_4_tvalid),
.m_axis_4_tready(m_axis_4_tready),
.m_axis_4_tlast (m_axis_4_tlast),
.nf0_q_size(nf0_q_size),
.nf1_q_size(nf1_q_size),
.nf2_q_size(nf2_q_size),
.nf3_q_size(nf3_q_size),
.dma_q_size(dma_q_size),
.bytes_stored(),
.pkt_stored(),
.bytes_removed_0(),
.bytes_removed_1(),
.bytes_removed_2(),
.bytes_removed_3(),
.bytes_removed_4(),
.pkt_removed_0(),
.pkt_removed_1(),
.pkt_removed_2(),
.pkt_removed_3(),
.pkt_removed_4(),
.bytes_dropped(bytes_dropped),
.pkt_dropped(pkt_dropped),
.S_AXI_AWADDR(S2_AXI_AWADDR),
.S_AXI_AWVALID(S2_AXI_AWVALID),
.S_AXI_WDATA(S2_AXI_WDATA),
.S_AXI_WSTRB(S2_AXI_WSTRB),
.S_AXI_WVALID(S2_AXI_WVALID),
.S_AXI_BREADY(S2_AXI_BREADY),
.S_AXI_ARADDR(S2_AXI_ARADDR),
.S_AXI_ARVALID(S2_AXI_ARVALID),
.S_AXI_RREADY(S2_AXI_RREADY),
.S_AXI_ARREADY(S2_AXI_ARREADY),
.S_AXI_RDATA(S2_AXI_RDATA),
.S_AXI_RRESP(S2_AXI_RRESP),
.S_AXI_RVALID(S2_AXI_RVALID),
.S_AXI_WREADY(S2_AXI_WREADY),
.S_AXI_BRESP(S2_AXI_BRESP),
.S_AXI_BVALID(S2_AXI_BVALID),
.S_AXI_AWREADY(S2_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn)
);
endmodule

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netpfga/minip4/simple_sume_switch/hw/hdl/top_tb.v
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//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// top_tb.v
//
// Module:
// top
//
// Author: Noa Zilberman
//
// Description:
// reference nic top module
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
`timescale 1ns / 100ps
module top_tb # (
parameter PL_SIM_FAST_LINK_TRAINING = "TRUE", // Simulation Speedup
parameter C_DATA_WIDTH = 256, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 32,
parameter integer USER_CLK2_FREQ = 4,
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = 0,
parameter AXISTEN_IF_RQ_PARITY_CHECK = 0,
parameter AXISTEN_IF_CC_PARITY_CHECK = 0,
parameter AXISTEN_IF_MC_RX_STRADDLE = 0,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = 0,
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h2FFFF
) (
);
parameter PCIE_PERIOD = 10;
parameter XPHY_PERIOD = 6.4;
parameter CORE_PERIOD = 4;
localparam TCQ = 1;
localparam BAR0AXI = 32'h40000000;
localparam BAR1AXI = 32'h10000000;
localparam BAR2AXI = 32'h20000000;
localparam BAR3AXI = 32'h30000000;
localparam BAR4AXI = 32'h40000000;
localparam BAR5AXI = 32'h50000000;
localparam BAR0SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR1SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR2SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR3SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR4SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR5SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam throttle_percent = 50;
reg sys_reset_n;
reg sys_clk;
wire sys_clkp,sys_clkn;
reg xphy_clk;
wire xphy_refclk_p,xphy_refclk_n;
reg clk_ref;
wire clk_ref_p,clk_ref_n;
//----------------------------------------------------------------------------------------------------------------//
// axis interface //
//----------------------------------------------------------------------------------------------------------------//
top_sim # (
.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING ),
.C_DATA_WIDTH (C_DATA_WIDTH ),
.KEEP_WIDTH (KEEP_WIDTH ),
.USER_CLK2_FREQ (USER_CLK2_FREQ ),
.REF_CLK_FREQ (REF_CLK_FREQ ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE ),
.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE ),
.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE ),
.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE ),
.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG ),
.AXISTEN_IF_RQ_PARITY_CHECK (AXISTEN_IF_RQ_PARITY_CHECK ),
.AXISTEN_IF_CC_PARITY_CHECK (AXISTEN_IF_CC_PARITY_CHECK ),
.AXISTEN_IF_MC_RX_STRADDLE (AXISTEN_IF_MC_RX_STRADDLE ),