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import simple_sume_switch from switch_calc

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Nico Schottelius 2019-07-23 15:17:53 +02:00
parent 706eac0e41
commit 0645646df5
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60
netpfga/minip4/simple_sume_switch/Makefile Normal file
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#
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# File:
# Makefile
#
# Project:
# reference projects
#
#
# Description:
# This makefile is used to generate and compile SDK project for NetFPGA reference projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
HW = hw
SW = sw/embedded/
TEST = test
all: clean
make -C ${HW} project
make -C ${HW} export_to_sdk
make -C ${SW} project
make -C ${SW} compile
make -C ${HW} load_elf
clean:
make -C ${HW} distclean
make -C ${SW} distclean
rm -rfv vivado*;\

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netpfga/minip4/simple_sume_switch/bitfiles/README Normal file
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#
# Copyright (c) 2017 Stephen Ibanez
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
This version allows the control plane to access all entries in the const
register

36
netpfga/minip4/simple_sume_switch/bitfiles/program_switch.sh Normal file
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#!/bin/bash
#
# Copyright (c) 2017 Stephen Ibanez
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Program the switch with the bit file and then configure the tables
${SUME_SDNET}/tools/program_switch.sh switch_calc.bit config_writes.sh

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netpfga/minip4/simple_sume_switch/hw/Makefile Normal file
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#
# Copyright (c) 2015 Noa Zilberman, Georgina Kalogeridou
# All rights reserved.
#
# File:
# Makefile
#
# Description:
# This makefile is used to generate and compile hw projects
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
PROJ = ${NF_PROJECT_NAME}
all:
@echo ""
@echo "NetFPGA-SUME Referece Project HW Makefile"
@echo ""
@echo "make TARGETS"
@echo "------------------------------------------------------"
@echo "project: Create hardware project"
@echo "sim: Run project simulation"
@echo "export_to_sdk: Export implemented project to sw/embedded"
@echo "load_elf: Load ELF file for specified project"
@echo ""
@echo "clean: Remove specified project"
@echo "distclean: Remove all generated projects"
@echo ""
.PHONY: clean project export_to_sdk load_elf
project: identifier
echo "Create reference project under folder /project";\
if test -d project/; then\
echo "Project already exists"; \
else \
vivado -mode batch -source tcl/${PROJ}.tcl;\
if [ -f patch/${PROJ}.patch ]; then\
patch -p1 < patch/${PROJ}.patch;\
fi;\
fi;\
projectgui:
echo "Create reference project under folder /project";\
if test -d project/; then\
echo "Project already exists"; \
else \
vivado -mode gui -source tcl/${PROJ}.tcl;\
if [ -f patch/${PROJ}.patch ]; then\
patch -p1 < patch/${PROJ}.patch;\
fi;\
fi;\
export_to_sdk: identifier
if test -d project; then\
echo "export ${PROJ} project to SDK"; \
vivado -mode tcl -source tcl/export_hardware.tcl -tclargs ${PROJ};\
else \
echo "Project ${PROJ} does not exist.";\
echo "Please run \"make project\" to create and build the project first";\
fi;\
load_elf:
@if [ ! -d ../bitfiles ]; then mkdir ../bitfiles; fi;
if test -d project; then\
echo "export ${PROJ} project to SDK"; \
vivado -mode tcl -source tcl/load_elf.tcl -tclargs ${PROJ};\
else \
echo "Project ${PROJ} does not exist.";\
echo "Please run \"make project\" to create and build the project first";\
fi;\
identifier:
rm -f ../hw/create_ip/id_rom16x32.coe
cp ${SUME_FOLDER}/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
echo 16028002 >> rom_data.txt
echo `${SUME_FOLDER}/run_tag.sh` >> rom_data.txt
echo 00000204 >> rom_data.txt
echo 0000FFFF >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
echo FFFF0000 >> rom_data.txt
cp ${SUME_FOLDER}/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
mv -f id_rom16x32.coe ../hw/create_ip/
mv -f rom_data.txt ../hw/create_ip/
sim: simclean identifier
cp -f $(NF_DESIGN_DIR)/test/reg_defines_${NF_PROJECT_NAME}.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_${NF_PROJECT_NAME}.py
vivado -mode batch -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
reg:
vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/${NF_PROJECT_NAME}_defines.tcl
vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/export_registers.tcl
cd ../sw/embedded/src && cp ${SUME_FOLDER}/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../
cd ../sw/embedded && cp ${SUME_FOLDER}/tools/scripts/python_parser.py . && python python_parser.py
cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_${NF_PROJECT_NAME}.py
simgui: simclean identifier
cp -f $(NF_DESIGN_DIR)/test/reg_defines_simple_sume_switch.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_simple_sume_switch.py
vivado -mode gui -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
simclean:
rm -rf proj_* vivado*.* *.*~ .Xil* $(NF_DESIGN_DIR)/hw/ip_repo/ $(NF_DESIGN_DIR)/hw/project/
rm -rf *[0-9]_{stim,expected,log}.axi
rm -f *.axi
rm -f portconfig.sim
rm -f seed
rm -f *.log
rm -f ../test/Makefile
rm -rf ../test/*.log
rm -rf ../test/*.axi
rm -rf ../test/seed
rm -rf ../test/*.sim
rm -rf ../test/proj_*
rm -rf ../test/ip_repo
rm -f ../test/vivado*.*
rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.py
rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.pyc
distclean: clean
clean: simclean
rm -rfv project;\
rm -rfv ../sw/embedded/project;\
rm -rfv vivado*;\
rm -rfv *.log;\
rm -rfv .Xil;\
rm -rfv ..rej;\
rm -rfv .srcs;\
rm -rfv webtalk*;\
rm -rfv *.*~;\
rm -rfv ip_repo;\
rm -rfv ip_proj;\
rm -rfv std;\

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netpfga/minip4/simple_sume_switch/hw/constraints/nf_sume_10g.xdc Normal file
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#
# Copyright (c) 2015 Noa Zilberman, Yury Audzevich
# All rights reserved.
#
# File:
# nf_sume_10g.xdc
#
# Author: Noa Zilberman
#
# Description:
# Location constraints for 4x 10GbE SFP+ interface used in reference
# projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# XGE-SFP0 -- SUME -- THE FIRST INTERFACE FROM THE TOP OF THE BOARD
set_property PACKAGE_PIN M18 [get_ports sfp0_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_disable]
set_property PACKAGE_PIN M19 [get_ports sfp0_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_fault]
set_property PACKAGE_PIN N18 [get_ports sfp0_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp0_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y39 [get_cells -hier -filter name=~*interface_0*gthe2_i]
# XGE-SFP1 -- SUME
set_property PACKAGE_PIN B31 [get_ports sfp1_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_disable]
set_property PACKAGE_PIN C26 [get_ports sfp1_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_fault]
set_property PACKAGE_PIN L19 [get_ports sfp1_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp1_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y38 [get_cells -hier -filter name=~*interface_1*gthe2_i]
#set_property LOC GTHE2_CHANNEL_X1Y38 [get_cells nf_10g_interface_1/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/ten_gig_eth_pcs_pma/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i]
# XGE-SFP2 -- SUME
set_property PACKAGE_PIN J38 [get_ports sfp2_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_disable]
set_property PACKAGE_PIN E39 [get_ports sfp2_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_fault]
set_property PACKAGE_PIN J37 [get_ports sfp2_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp2_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y37 [get_cells -hier -filter name=~*interface_2*gthe2_i]
# XGE-SFP3 -- SUME -- FIRST FROM THE BOTTOM (to PCIe)
set_property PACKAGE_PIN L21 [get_ports sfp3_tx_disable]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_disable]
set_property PACKAGE_PIN J26 [get_ports sfp3_tx_fault]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_fault]
set_property PACKAGE_PIN H36 [get_ports sfp3_tx_abs]
set_property IOSTANDARD LVCMOS15 [get_ports sfp3_tx_abs]
set_property LOC GTHE2_CHANNEL_X1Y36 [get_cells -hier -filter name=~*interface_3*gthe2_i]
#set_property LOC GTHE2_CHANNEL_X1Y36 [get_cells nf_10g_interface_3/inst/nf_10g_interface_block_i/axi_10g_ethernet_i/inst/ten_gig_eth_pcs_pma/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_gth_10gbaser_i/gthe2_i]
## -- SFP clocks
## -- The clock is supplied by Si5324 chip;
## -- the clock is configured through microblaze.
set_property PACKAGE_PIN E10 [get_ports xphy_refclk_p]
set_property PACKAGE_PIN E9 [get_ports xphy_refclk_n]
create_clock -period 6.400 [get_ports xphy_refclk_p]
#create_clock -period 6.400 -name xgemac_clk_156 [get_ports xphy_refclk_p]
# XGE TX/RX LEDs
# GRN - TX
# YLW - RX
set_property PACKAGE_PIN G13 [get_ports sfp0_tx_led]
set_property PACKAGE_PIN AL22 [get_ports sfp1_tx_led]
set_property PACKAGE_PIN AY18 [get_ports sfp2_tx_led]
set_property PACKAGE_PIN P31 [get_ports sfp3_tx_led]
set_property PACKAGE_PIN L15 [get_ports sfp0_rx_led]
set_property PACKAGE_PIN BA20 [get_ports sfp1_rx_led]
set_property PACKAGE_PIN AY17 [get_ports sfp2_rx_led]
set_property PACKAGE_PIN K32 [get_ports sfp3_rx_led]
set_property IOSTANDARD LVCMOS15 [get_ports sfp?_?x_led]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets nf_10g_shared_i/inst/refclk]
## Timing Constraints
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_0*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_0*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_1*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_1*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_2*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_2*gthe2_i/TXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_3*gthe2_i/RXOUTCLK]
create_clock -period 3.103 [get_pins -hier -filter name=~*interface_3*gthe2_i/TXOUTCLK]
## Timing Constraints
###################
## Other constraints
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks clk_250mhz_mux_x0y1] -to [get_clocks clk_125mhz_x0y1]
set_false_path -from [get_clocks clk_125mhz_x0y1] -to [get_clocks clk_250mhz_mux_x0y1]
set_false_path -from [get_clocks userclk1] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks axi_clk]
set_false_path -from [get_clocks axi_clk] -to [get_clocks userclk1]
set_false_path -from [get_clocks userclk1] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks userclk1]
set_false_path -from [get_clocks -filter name=~*interface_*gthe2_i/RXOUTCLK] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks -filter name=~*interface_*gthe2_i/RXOUTCLK]
set_false_path -from [get_clocks -filter name=~*interface_*gthe2_i/TXOUTCLK] -to [get_clocks xphy_refclk_p]
set_false_path -from [get_clocks xphy_refclk_p] -to [get_clocks -filter name=~*interface_*gthe2_i/TXOUTCLK]

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netpfga/minip4/simple_sume_switch/hw/constraints/nf_sume_general.xdc Normal file
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# Copyright (c) 2015 Tinghui Wang
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# File:
# nf_sume_general.xdc
#
# Author:
# Tinghui Wang (Steve)
# Modified by:
# Noa Zilberman
#
# Description:
# System general constraints for NetFPGA-SUME board.
# The file includes constraints for:
# - Master FPGA 200MHz clock (fpga_sysclk)
# - Main I2C Bus (iic_fpga, si5324_rst_n)
# - UART (115200-8N1)
# - Btn0 is used as system sys_reset_n (active high)
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
## -- The following two properties should be set for every design
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
## -- PCIe Transceiver clock (100 MHz)
set_property LOC IBUFDS_GTE2_X1Y11 [get_cells IBUFDS_GTE2_inst]
create_clock -period 10.000 -name sys_clk -add [get_pins -hier -filter name=~*IBUFDS_GTE2_inst/O]
create_clock -period 10.000 -name sys_clkp -waveform {0.000 5.000} [get_ports sys_clkp]
## -- PCIe sys reset
set_property PACKAGE_PIN AY35 [get_ports sys_reset_n]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset_n]
set_property PULLUP true [get_ports sys_reset_n]
set_false_path -from [get_ports sys_reset_n]
# 200MHz System Clock -- SUME
set_property PACKAGE_PIN H19 [get_ports fpga_sysclk_p]
set_property VCCAUX_IO DONTCARE [get_ports fpga_sysclk_p]
set_property IOSTANDARD LVDS [get_ports fpga_sysclk_p]
set_property IOSTANDARD LVDS [get_ports fpga_sysclk_n]
#create_clock -period 5.00 [get_ports {axi_clocking_i/s_axi_aclk}]
create_clock -period 5.000 -name fpga_sysclk_p -waveform {0.000 2.500} [get_ports fpga_sysclk_p]
## -- 200MHz & 100MHz clks
create_clock -period 5.000 -name clk_200 -add [get_pins -hier -filter name=~*axi_clocking_i*clk_wiz_i/clk_out1]
create_clock -period 10.000 -name axi_clk -add [get_pins -hier -filter name=~*axi_lite_bufg0/O]
# Main I2C Bus - 100KHz - SUME
set_property IOSTANDARD LVCMOS18 [get_ports i2c_clk]
set_property SLEW SLOW [get_ports i2c_clk]
set_property DRIVE 16 [get_ports i2c_clk]
set_property PULLUP true [get_ports i2c_clk]
set_property PACKAGE_PIN AK24 [get_ports i2c_clk]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_data]
set_property SLEW SLOW [get_ports i2c_data]
set_property DRIVE 16 [get_ports i2c_data]
set_property PULLUP true [get_ports i2c_data]
set_property PACKAGE_PIN AK25 [get_ports i2c_data]
# i2c_reset[0] - i2c_mux reset - high active
# i2c_reset[1] - si5324 reset - high active
set_property SLEW SLOW [get_ports {i2c_reset[*]}]
set_property DRIVE 16 [get_ports {i2c_reset[*]}]
set_property PACKAGE_PIN AM39 [get_ports {i2c_reset[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {i2c_reset[0]}]
set_property PACKAGE_PIN BA29 [get_ports {i2c_reset[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {i2c_reset[1]}]
## -- USER LEDS
set_property PACKAGE_PIN AR22 [get_ports {leds[0]}]
set_property PACKAGE_PIN AR23 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[1]}]
set_false_path -to [get_ports -filter NAME=~led*]
# UART - 115200 8-1 no parity
set_property PACKAGE_PIN AY19 [get_ports uart_rxd]
set_property PACKAGE_PIN BA19 [get_ports uart_txd]
set_property IOSTANDARD LVCMOS15 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS15 [get_ports uart_txd]
#False paths
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {control_sub_i/dma_sub/pcie3_7x_1/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/pipe_txoutclk_out}]
# Bitfile Generation
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_false_path -from [get_clocks sys_clk] -to [get_clocks clk_200]
set_false_path -from [get_clocks axi_clk] -to [get_clocks clk_200]
set_false_path -from [get_clocks clk_200] -to [get_clocks axi_clk]

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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
# Set variables
# CORE CONFIG parameters
set sharedLogic "FALSE"
set tdataWidth 256
set convWidth [expr $tdataWidth/8]
if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
set supportLevel 1
} else {
set supportLevel 0
}
create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_nonshared
set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_nonshared]
set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_nonshared]
set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_nonshared.xci]
reset_target all [get_ips axi_10g_ethernet_nonshared]
generate_target all [get_ips axi_10g_ethernet_nonshared]
create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_status
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Performance_Options {First_Word_Fall_Through}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Input_Data_Width {458} CONFIG.Input_Depth {16}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Reset_Pin {false}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Output_Data_Width {458} CONFIG.Output_Depth {16}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Flags_Reset_Value {0}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Use_Dout_Reset {false}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Write_Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Read_Data_Count_Width {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {15}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Full_Threshold_Negate_Value {14}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Empty_Threshold_Assert_Value {4}] [get_ips fifo_generator_status]
set_property -dict [list CONFIG.Empty_Threshold_Negate_Value {5}] [get_ips fifo_generator_status]
set_property generate_synth_checkpoint false [get_files fifo_generator_status.xci]
reset_target all [get_ips fifo_generator_status]
generate_target all [get_ips fifo_generator_status]
create_ip -name util_vector_logic -vendor xilinx.com -library ip -version 2.0 -module_name inverter_0
set_property -dict [list CONFIG.C_SIZE {1}] [get_ips inverter_0]
set_property -dict [list CONFIG.C_OPERATION {not}] [get_ips inverter_0]
set_property generate_synth_checkpoint false [get_files inverter_0.xci]
reset_target all [get_ips inverter_0]
generate_target all [get_ips inverter_0]
create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_1_9
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM} CONFIG.Performance_Options {First_Word_Fall_Through} CONFIG.Input_Data_Width {1} CONFIG.Input_Depth {16} CONFIG.Output_Data_Width {1} CONFIG.Output_Depth {16} CONFIG.Data_Count_Width {4} CONFIG.Write_Data_Count_Width {4} CONFIG.Read_Data_Count_Width {4} CONFIG.Full_Threshold_Assert_Value {13} CONFIG.Full_Threshold_Negate_Value {12}] [get_ips fifo_generator_1_9]
set_property generate_synth_checkpoint false [get_files fifo_generator_1_9.xci]
reset_target all [get_ips fifo_generator_1_9]
generate_target all [get_ips fifo_generator_1_9]

59
netpfga/minip4/simple_sume_switch/hw/create_ip/nf_10ge_interface_shared.tcl Normal file
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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
# Set variables.
## CORE CONFIGURATION parameters
# should correspond to hdl params
set sharedLogic "TRUE"
set tdataWidth 256
set convWidth [expr $tdataWidth/8]
if { $sharedLogic eq "True" || $sharedLogic eq "TRUE" || $sharedLogic eq "true" } {
set supportLevel 1
} else {
set supportLevel 0
}
create_ip -name axi_10g_ethernet -vendor xilinx.com -library ip -version 3.1 -module_name axi_10g_ethernet_shared
set_property -dict [list CONFIG.Management_Interface {false}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.base_kr {BASE-R}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.SupportLevel $supportLevel] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.autonegotiation {0}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.fec {0}] [get_ips axi_10g_ethernet_shared]
set_property -dict [list CONFIG.Statistics_Gathering {0}] [get_ips axi_10g_ethernet_shared]
set_property generate_synth_checkpoint false [get_files axi_10g_ethernet_shared.xci]
reset_target all [get_ips axi_10g_ethernet_shared]
generate_target all [get_ips axi_10g_ethernet_shared]

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netpfga/minip4/simple_sume_switch/hw/create_ip/nf_sume_sdnet.tcl.bak Normal file
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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 1.1 -module_name axis_data_fifo_0
set_property -dict [list CONFIG.TDATA_NUM_BYTES {32} CONFIG.TUSER_WIDTH {160} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1}] [get_ips axis_data_fifo_0]
set_property generate_synth_checkpoint false [get_files axis_data_fifo_0.xci]
reset_target all [get_ips axis_data_fifo_0]
generate_target all [get_ips axis_data_fifo_0]

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//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// axi_clocking.v
//
// Module:
// axi_clocking
//
// Author: Noa Zilberman
//
// Description:
// Sharable clocking resources for NetFPGA SUME
//
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
`timescale 1ps / 1ps
(* dont_touch = "yes" *)
module axi_clocking
(
// Inputs
input clk_in_p,
input clk_in_n,
input resetn,
// Status outputs
// IBUFDS 200MHz
output locked,
output clk_200
);
// Signal declarations
wire s_axi_dcm_aclk0;
wire clkfbout;
// 200MHz differencial into single-rail
IBUFDS clkin1_buf
(.O (clkin1),
.I (clk_in_p),
.IB (clk_in_n)
);
clk_wiz_ip clk_wiz_i
(
// Clock in ports
.clk_in1(clkin1), // input clk_in1
// Clock out ports
.clk_out1(clk_200), // output clk_out1
// Status and control signals
.resetn(resetn), // input resetn
.locked(locked));
endmodule

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`timescale 1ns / 1ps
//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// nf_datapath.v
//
// Module:
// nf_datapath
//
// Author: Noa Zilberman
//
// Description:
// NetFPGA user data path wrapper, wrapping input arbiter, output port lookup and output queues
//
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
module nf_datapath #(
//Slave AXI parameters
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_BASEADDR = 32'h00000000,
// Master AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH=256,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_M_AXIS_TUSER_WIDTH=128,
parameter C_S_AXIS_TUSER_WIDTH=128,
parameter NUM_QUEUES=5,
parameter DIGEST_WIDTH =80
)
(
//Datapath clock
input axis_aclk,
input axis_resetn,
//Registers clock
input axi_aclk,
input axi_resetn,
// Slave AXI Ports
input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_AWADDR,
input S0_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S0_AXI_WSTRB,
input S0_AXI_WVALID,
input S0_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S0_AXI_ARADDR,
input S0_AXI_ARVALID,
input S0_AXI_RREADY,
output S0_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S0_AXI_RDATA,
output [1 : 0] S0_AXI_RRESP,
output S0_AXI_RVALID,
output S0_AXI_WREADY,
output [1 :0] S0_AXI_BRESP,
output S0_AXI_BVALID,
output S0_AXI_AWREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_AWADDR,
input S1_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S1_AXI_WSTRB,
input S1_AXI_WVALID,
input S1_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S1_AXI_ARADDR,
input S1_AXI_ARVALID,
input S1_AXI_RREADY,
output S1_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S1_AXI_RDATA,
output [1 : 0] S1_AXI_RRESP,
output S1_AXI_RVALID,
output S1_AXI_WREADY,
output [1 :0] S1_AXI_BRESP,
output S1_AXI_BVALID,
output S1_AXI_AWREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_AWADDR,
input S2_AXI_AWVALID,
input [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_WDATA,
input [C_S_AXI_DATA_WIDTH/8-1 : 0] S2_AXI_WSTRB,
input S2_AXI_WVALID,
input S2_AXI_BREADY,
input [C_S_AXI_ADDR_WIDTH-1 : 0] S2_AXI_ARADDR,
input S2_AXI_ARVALID,
input S2_AXI_RREADY,
output S2_AXI_ARREADY,
output [C_S_AXI_DATA_WIDTH-1 : 0] S2_AXI_RDATA,
output [1 : 0] S2_AXI_RRESP,
output S2_AXI_RVALID,
output S2_AXI_WREADY,
output [1 :0] S2_AXI_BRESP,
output S2_AXI_BVALID,
output S2_AXI_AWREADY,
// Slave Stream Ports (interface from Rx queues)
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_0_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_0_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_0_tuser,
input s_axis_0_tvalid,
output s_axis_0_tready,
input s_axis_0_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_1_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_1_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_1_tuser,
input s_axis_1_tvalid,
output s_axis_1_tready,
input s_axis_1_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_2_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_2_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_2_tuser,
input s_axis_2_tvalid,
output s_axis_2_tready,
input s_axis_2_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_3_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_3_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_3_tuser,
input s_axis_3_tvalid,
output s_axis_3_tready,
input s_axis_3_tlast,
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_4_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_4_tkeep,
input [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_4_tuser,
input s_axis_4_tvalid,
output s_axis_4_tready,
input s_axis_4_tlast,
// Master Stream Ports (interface to TX queues)
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_0_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_0_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_0_tuser,
output m_axis_0_tvalid,
input m_axis_0_tready,
output m_axis_0_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_1_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_1_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_1_tuser,
output m_axis_1_tvalid,
input m_axis_1_tready,
output m_axis_1_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_2_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_2_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_2_tuser,
output m_axis_2_tvalid,
input m_axis_2_tready,
output m_axis_2_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_3_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_3_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_3_tuser,
output m_axis_3_tvalid,
input m_axis_3_tready,
output m_axis_3_tlast,
output [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_4_tdata,
output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_4_tkeep,
output [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_4_tuser,
output m_axis_4_tvalid,
input m_axis_4_tready,
output m_axis_4_tlast
);
localparam C_AXIS_TUSER_DIGEST_WIDTH = 304;
//internal connectivity
(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_opl_tdata;
(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_opl_tkeep;
(* mark_debug = "true" *) wire [C_AXIS_TUSER_DIGEST_WIDTH-1:0] m_axis_opl_tuser;
(* mark_debug = "true" *) wire m_axis_opl_tvalid;
(* mark_debug = "true" *) wire m_axis_opl_tready;
(* mark_debug = "true" *) wire m_axis_opl_tlast;
(* mark_debug = "true" *) wire [C_M_AXIS_DATA_WIDTH - 1:0] s_axis_opl_tdata;
(* mark_debug = "true" *) wire [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_opl_tkeep;
(* mark_debug = "true" *) wire [C_M_AXIS_TUSER_WIDTH-1:0] s_axis_opl_tuser;
(* mark_debug = "true" *) wire s_axis_opl_tvalid;
(* mark_debug = "true" *) wire s_axis_opl_tready;
(* mark_debug = "true" *) wire s_axis_opl_tlast;
localparam Q_SIZE_WIDTH = 16;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf0_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf1_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf2_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] nf3_q_size;
(* mark_debug = "true" *) wire [Q_SIZE_WIDTH-1:0] dma_q_size;
//Input Arbiter
input_arbiter_ip
input_arbiter_v1_0 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.m_axis_tdata (s_axis_opl_tdata),
.m_axis_tkeep (s_axis_opl_tkeep),
.m_axis_tuser (s_axis_opl_tuser),
.m_axis_tvalid(s_axis_opl_tvalid),
.m_axis_tready(s_axis_opl_tready),
.m_axis_tlast (s_axis_opl_tlast),
.s_axis_0_tdata (s_axis_0_tdata),
.s_axis_0_tkeep (s_axis_0_tkeep),
.s_axis_0_tuser (s_axis_0_tuser),
.s_axis_0_tvalid(s_axis_0_tvalid),
.s_axis_0_tready(s_axis_0_tready),
.s_axis_0_tlast (s_axis_0_tlast),
.s_axis_1_tdata (s_axis_1_tdata),
.s_axis_1_tkeep (s_axis_1_tkeep),
.s_axis_1_tuser (s_axis_1_tuser),
.s_axis_1_tvalid(s_axis_1_tvalid),
.s_axis_1_tready(s_axis_1_tready),
.s_axis_1_tlast (s_axis_1_tlast),
.s_axis_2_tdata (s_axis_2_tdata),
.s_axis_2_tkeep (s_axis_2_tkeep),
.s_axis_2_tuser (s_axis_2_tuser),
.s_axis_2_tvalid(s_axis_2_tvalid),
.s_axis_2_tready(s_axis_2_tready),
.s_axis_2_tlast (s_axis_2_tlast),
.s_axis_3_tdata (s_axis_3_tdata),
.s_axis_3_tkeep (s_axis_3_tkeep),
.s_axis_3_tuser (s_axis_3_tuser),
.s_axis_3_tvalid(s_axis_3_tvalid),
.s_axis_3_tready(s_axis_3_tready),
.s_axis_3_tlast (s_axis_3_tlast),
.s_axis_4_tdata (s_axis_4_tdata),
.s_axis_4_tkeep (s_axis_4_tkeep),
.s_axis_4_tuser (s_axis_4_tuser),
.s_axis_4_tvalid(s_axis_4_tvalid),
.s_axis_4_tready(s_axis_4_tready),
.s_axis_4_tlast (s_axis_4_tlast),
.S_AXI_AWADDR(S0_AXI_AWADDR),
.S_AXI_AWVALID(S0_AXI_AWVALID),
.S_AXI_WDATA(S0_AXI_WDATA),
.S_AXI_WSTRB(S0_AXI_WSTRB),
.S_AXI_WVALID(S0_AXI_WVALID),
.S_AXI_BREADY(S0_AXI_BREADY),
.S_AXI_ARADDR(S0_AXI_ARADDR),
.S_AXI_ARVALID(S0_AXI_ARVALID),
.S_AXI_RREADY(S0_AXI_RREADY),
.S_AXI_ARREADY(S0_AXI_ARREADY),
.S_AXI_RDATA(S0_AXI_RDATA),
.S_AXI_RRESP(S0_AXI_RRESP),
.S_AXI_RVALID(S0_AXI_RVALID),
.S_AXI_WREADY(S0_AXI_WREADY),
.S_AXI_BRESP(S0_AXI_BRESP),
.S_AXI_BVALID(S0_AXI_BVALID),
.S_AXI_AWREADY(S0_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn),
.pkt_fwd()
);
// SUME SDNet Module
nf_sume_sdnet_ip
nf_sume_sdnet_wrapper_1 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.m_axis_tdata (m_axis_opl_tdata),
.m_axis_tkeep (m_axis_opl_tkeep),
.m_axis_tuser (m_axis_opl_tuser),
.m_axis_tvalid(m_axis_opl_tvalid),
.m_axis_tready(m_axis_opl_tready),
.m_axis_tlast (m_axis_opl_tlast),
.s_axis_tdata (s_axis_opl_tdata),
.s_axis_tkeep (s_axis_opl_tkeep),
.s_axis_tuser ({dma_q_size, nf3_q_size, nf2_q_size, nf1_q_size, nf0_q_size, s_axis_opl_tuser[C_M_AXIS_TUSER_WIDTH-DIGEST_WIDTH-1:0]}),
.s_axis_tvalid(s_axis_opl_tvalid),
.s_axis_tready(s_axis_opl_tready),
.s_axis_tlast (s_axis_opl_tlast),
.S_AXI_AWADDR(S1_AXI_AWADDR),
.S_AXI_AWVALID(S1_AXI_AWVALID),
.S_AXI_WDATA(S1_AXI_WDATA),
.S_AXI_WSTRB(S1_AXI_WSTRB),
.S_AXI_WVALID(S1_AXI_WVALID),
.S_AXI_BREADY(S1_AXI_BREADY),
.S_AXI_ARADDR(S1_AXI_ARADDR),
.S_AXI_ARVALID(S1_AXI_ARVALID),
.S_AXI_RREADY(S1_AXI_RREADY),
.S_AXI_ARREADY(S1_AXI_ARREADY),
.S_AXI_RDATA(S1_AXI_RDATA),
.S_AXI_RRESP(S1_AXI_RRESP),
.S_AXI_RVALID(S1_AXI_RVALID),
.S_AXI_WREADY(S1_AXI_WREADY),
.S_AXI_BRESP(S1_AXI_BRESP),
.S_AXI_BVALID(S1_AXI_BVALID),
.S_AXI_AWREADY(S1_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn)
);
(* mark_debug = "true" *) wire [C_S_AXI_DATA_WIDTH-1:0] bytes_dropped;
(* mark_debug = "true" *) wire [5-1:0] pkt_dropped;
// assign nf0_q_size = 'd12;
// assign nf1_q_size = 'd13;
// assign nf2_q_size = 'd14;
// assign nf3_q_size = 'd15;
// assign dma_q_size = 'd16;
//Output queues
sss_output_queues_ip
bram_output_queues_1 (
.axis_aclk(axis_aclk),
.axis_resetn(axis_resetn),
.s_axis_tdata (m_axis_opl_tdata),
.s_axis_tkeep (m_axis_opl_tkeep),
.s_axis_tuser (m_axis_opl_tuser),
.s_axis_tvalid (m_axis_opl_tvalid),
.s_axis_tready (m_axis_opl_tready),
.s_axis_tlast (m_axis_opl_tlast),
.m_axis_0_tdata (m_axis_0_tdata),
.m_axis_0_tkeep (m_axis_0_tkeep),
.m_axis_0_tuser (m_axis_0_tuser),
.m_axis_0_tvalid(m_axis_0_tvalid),
.m_axis_0_tready(m_axis_0_tready),
.m_axis_0_tlast (m_axis_0_tlast),
.m_axis_1_tdata (m_axis_1_tdata),
.m_axis_1_tkeep (m_axis_1_tkeep),
.m_axis_1_tuser (m_axis_1_tuser),
.m_axis_1_tvalid(m_axis_1_tvalid),
.m_axis_1_tready(m_axis_1_tready),
.m_axis_1_tlast (m_axis_1_tlast),
.m_axis_2_tdata (m_axis_2_tdata),
.m_axis_2_tkeep (m_axis_2_tkeep),
.m_axis_2_tuser (m_axis_2_tuser),
.m_axis_2_tvalid(m_axis_2_tvalid),
.m_axis_2_tready(m_axis_2_tready),
.m_axis_2_tlast (m_axis_2_tlast),
.m_axis_3_tdata (m_axis_3_tdata),
.m_axis_3_tkeep (m_axis_3_tkeep),
.m_axis_3_tuser (m_axis_3_tuser),
.m_axis_3_tvalid(m_axis_3_tvalid),
.m_axis_3_tready(m_axis_3_tready),
.m_axis_3_tlast (m_axis_3_tlast),
.m_axis_4_tdata (m_axis_4_tdata),
.m_axis_4_tkeep (m_axis_4_tkeep),
.m_axis_4_tuser (m_axis_4_tuser),
.m_axis_4_tvalid(m_axis_4_tvalid),
.m_axis_4_tready(m_axis_4_tready),
.m_axis_4_tlast (m_axis_4_tlast),
.nf0_q_size(nf0_q_size),
.nf1_q_size(nf1_q_size),
.nf2_q_size(nf2_q_size),
.nf3_q_size(nf3_q_size),
.dma_q_size(dma_q_size),
.bytes_stored(),
.pkt_stored(),
.bytes_removed_0(),
.bytes_removed_1(),
.bytes_removed_2(),
.bytes_removed_3(),
.bytes_removed_4(),
.pkt_removed_0(),
.pkt_removed_1(),
.pkt_removed_2(),
.pkt_removed_3(),
.pkt_removed_4(),
.bytes_dropped(bytes_dropped),
.pkt_dropped(pkt_dropped),
.S_AXI_AWADDR(S2_AXI_AWADDR),
.S_AXI_AWVALID(S2_AXI_AWVALID),
.S_AXI_WDATA(S2_AXI_WDATA),
.S_AXI_WSTRB(S2_AXI_WSTRB),
.S_AXI_WVALID(S2_AXI_WVALID),
.S_AXI_BREADY(S2_AXI_BREADY),
.S_AXI_ARADDR(S2_AXI_ARADDR),
.S_AXI_ARVALID(S2_AXI_ARVALID),
.S_AXI_RREADY(S2_AXI_RREADY),
.S_AXI_ARREADY(S2_AXI_ARREADY),
.S_AXI_RDATA(S2_AXI_RDATA),
.S_AXI_RRESP(S2_AXI_RRESP),
.S_AXI_RVALID(S2_AXI_RVALID),
.S_AXI_WREADY(S2_AXI_WREADY),
.S_AXI_BRESP(S2_AXI_BRESP),
.S_AXI_BVALID(S2_AXI_BVALID),
.S_AXI_AWREADY(S2_AXI_AWREADY),
.S_AXI_ACLK (axi_aclk),
.S_AXI_ARESETN(axi_resetn)
);
endmodule

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//-
// Copyright (c) 2015 Noa Zilberman
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// File:
// top_tb.v
//
// Module:
// top
//
// Author: Noa Zilberman
//
// Description:
// reference nic top module
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
//
`timescale 1ns / 100ps
module top_tb # (
parameter PL_SIM_FAST_LINK_TRAINING = "TRUE", // Simulation Speedup
parameter C_DATA_WIDTH = 256, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 32,
parameter integer USER_CLK2_FREQ = 4,
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = 0,
parameter AXISTEN_IF_RQ_PARITY_CHECK = 0,
parameter AXISTEN_IF_CC_PARITY_CHECK = 0,
parameter AXISTEN_IF_MC_RX_STRADDLE = 0,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = 0,
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h2FFFF
) (
);
parameter PCIE_PERIOD = 10;
parameter XPHY_PERIOD = 6.4;
parameter CORE_PERIOD = 4;
localparam TCQ = 1;
localparam BAR0AXI = 32'h40000000;
localparam BAR1AXI = 32'h10000000;
localparam BAR2AXI = 32'h20000000;
localparam BAR3AXI = 32'h30000000;
localparam BAR4AXI = 32'h40000000;
localparam BAR5AXI = 32'h50000000;
localparam BAR0SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR1SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR2SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR3SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR4SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam BAR5SIZE = 64'hFFFF_FFFF_FFFF_FF80;
localparam throttle_percent = 50;
reg sys_reset_n;
reg sys_clk;
wire sys_clkp,sys_clkn;
reg xphy_clk;
wire xphy_refclk_p,xphy_refclk_n;
reg clk_ref;
wire clk_ref_p,clk_ref_n;
//----------------------------------------------------------------------------------------------------------------//
// axis interface //
//----------------------------------------------------------------------------------------------------------------//
top_sim # (
.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING ),
.C_DATA_WIDTH (C_DATA_WIDTH ),
.KEEP_WIDTH (KEEP_WIDTH ),
.USER_CLK2_FREQ (USER_CLK2_FREQ ),
.REF_CLK_FREQ (REF_CLK_FREQ ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE ),
.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE ),
.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE ),
.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE ),
.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG ),
.AXISTEN_IF_RQ_PARITY_CHECK (AXISTEN_IF_RQ_PARITY_CHECK ),
.AXISTEN_IF_CC_PARITY_CHECK (AXISTEN_IF_CC_PARITY_CHECK ),
.AXISTEN_IF_MC_RX_STRADDLE (AXISTEN_IF_MC_RX_STRADDLE ),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC ),
.AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE )
) top_sim (
//PCI Express
.pcie_7x_mgt_rxn(pcie_7x_mgt_rxn),
.pcie_7x_mgt_rxp(pcie_7x_mgt_rxp),
.pcie_7x_mgt_txn(pcie_7x_mgt_txn),
.pcie_7x_mgt_txp(pcie_7x_mgt_txp),
//10G Interface
.sfp0_rx_p(rxp),
.sfp0_rx_n(rxn),
.sfp0_tx_p(txp),
.sfp0_tx_n(txn),
// PCIe Clock
.sys_clkp(sys_clkp),
.sys_clkn(sys_clkn),
//200MHz Clock
.fpga_sysclk_p(clk_ref_p),
.fpga_sysclk_n(clk_ref_n),
//-SI5324 I2C programming interface
.i2c_clk (i2c_clk),
.i2c_data (i2c_data),
.i2c_reset(si5324_rst_n),
// 156.25 MHz clock in
.xphy_refclk_p (xphy_refclk_p),
.xphy_refclk_n (xphy_refclk_n),
.led_0(led_0),
.led_1(led_1),
.sys_reset_n(sys_reset_n)
);
//Reset handling
// Important! polarity here is opposite the one in the actual design
initial begin
sys_reset_n = 1'b0;
#(CORE_PERIOD * 200);
sys_reset_n = 1'b1;
$display("Reset Deasserted");
end
//Clock generation
initial begin
sys_clk = 1'b0;
#(PCIE_PERIOD/2);
forever
#(PCIE_PERIOD/2) sys_clk = ~sys_clk;
end
assign sys_clkp = sys_clk;
assign sys_clkn = ~sys_clk;
initial begin
xphy_clk = 1'b0;
#(XPHY_PERIOD/2);
forever
#(XPHY_PERIOD/2) xphy_clk = ~xphy_clk;
end
assign xphy_refclk_p = xphy_clk;
assign xphy_refclk_n = ~xphy_clk;
initial begin
clk_ref = 1'b0;
#(CORE_PERIOD/2);
forever
#(CORE_PERIOD/2) clk_ref = ~clk_ref;
end
assign clk_ref_p = clk_ref;
assign clk_ref_n = ~clk_ref;
endmodule

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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
return 1
}
################################################################
# START
################################################################
# CHANGE DESIGN NAME HERE
set design_name control_sub
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Hierarchical cell: microblaze_0_local_memory
proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
# Create pins
create_bd_pin -dir I -type clk LMB_Clk
create_bd_pin -dir I -from 0 -to 0 -type rst LMB_Rst
# Create instance: dlmb_bram_if_cntlr, and set properties
set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
set_property -dict [ list CONFIG.C_ECC {0} ] $dlmb_bram_if_cntlr
# Create instance: dlmb_v10, and set properties
set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
# Create instance: ilmb_bram_if_cntlr, and set properties
set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
set_property -dict [ list CONFIG.C_ECC {0} ] $ilmb_bram_if_cntlr
# Create instance: ilmb_v10, and set properties
set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
# Create instance: lmb_bram, and set properties
set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ]
set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller} ] $lmb_bram
# Create interface connections
connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
# Create port connections
connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins LMB_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: mbsys
proc create_hier_cell_mbsys { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_mbsys() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
# Create pins
create_bd_pin -dir I -type clk Clk
create_bd_pin -dir I -from 0 -to 0 In0
create_bd_pin -dir I -from 0 -to 0 In1
create_bd_pin -dir I dcm_locked
create_bd_pin -dir I -type rst ext_reset_in
create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn
# Create instance: mdm_1, and set properties
set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
# Create instance: microblaze_0, and set properties
set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
set_property -dict [ list CONFIG.C_DEBUG_ENABLED {1} CONFIG.C_D_AXI {1} CONFIG.C_D_LMB {1} CONFIG.C_I_LMB {1} ] $microblaze_0
# Create instance: microblaze_0_axi_intc, and set properties
set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
set_property -dict [ list CONFIG.C_HAS_FAST {1} ] $microblaze_0_axi_intc
# Create instance: microblaze_0_axi_periph, and set properties
set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
set_property -dict [ list CONFIG.NUM_MI {3} ] $microblaze_0_axi_periph
# Create instance: microblaze_0_local_memory
create_hier_cell_microblaze_0_local_memory $hier_obj microblaze_0_local_memory
# Create instance: microblaze_0_xlconcat, and set properties
set microblaze_0_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_xlconcat ]
# Create instance: rst_clk_wiz_1_100M, and set properties
set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ]
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M01_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M02_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
# Create port connections
connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins microblaze_0_xlconcat/In0]
connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins microblaze_0_xlconcat/In1]
connect_bd_net -net clk_wiz_1_locked [get_bd_pins dcm_locked] [get_bd_pins rst_clk_wiz_1_100M/dcm_locked]
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst]
connect_bd_net -net microblaze_0_Clk [get_bd_pins Clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/processor_clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk]
connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_xlconcat/dout]
connect_bd_net -net reset_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/LMB_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset]
connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn]
connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_axi_intc/processor_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_reset]
connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: nf_mbsys
proc create_hier_cell_nf_mbsys { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_nf_mbsys() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart
# Create pins
create_bd_pin -dir O -from 1 -to 0 iic_reset
create_bd_pin -dir I -type rst reset
create_bd_pin -dir I -type clk sysclk
# Create instance: axi_iic_0, and set properties
set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0
# Create instance: clk_wiz_1, and set properties
set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_1 ]
# set_property -dict [ list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.PRIM_SOURCE {No_buffer} ] $clk_wiz_1
# config 100MHz input clk
set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.CLKIN1_JITTER_PS {100.0} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
CONFIG.MMCM_CLKIN1_PERIOD {10.0} CONFIG.CLKOUT1_JITTER {130.958} \
CONFIG.CLKOUT1_PHASE_ERROR {98.575}] $clk_wiz_1
# Create instance: mbsys
create_hier_cell_mbsys $hier_obj mbsys
# Create interface connections
connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_pins iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_pins uart] [get_bd_intf_pins axi_uartlite_0/UART]
connect_bd_intf_net -intf_net mbsys_M01_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins mbsys/M01_AXI]
connect_bd_intf_net -intf_net mbsys_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins mbsys/M02_AXI]
# Create port connections
connect_bd_net -net axi_iic_0_gpo [get_bd_pins iic_reset] [get_bd_pins axi_iic_0/gpo]
connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/In0]
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/In1]
connect_bd_net -net clk_wiz_1_locked [get_bd_pins clk_wiz_1/locked] [get_bd_pins mbsys/dcm_locked]
connect_bd_net -net mbsys_peripheral_aresetn [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mbsys/peripheral_aresetn]
connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins mbsys/Clk]
connect_bd_net -net reset_1 [get_bd_pins reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins mbsys/ext_reset_in]
connect_bd_net -net sysclk_1 [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: dma_sub
proc create_hier_cell_dma_sub { parentCell nameHier } {
if { $parentCell eq "" || $nameHier eq "" } {
puts "ERROR: create_hier_cell_dma_sub() - Empty argument(s)!"
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx
# Create pins
create_bd_pin -dir I -type clk axi_lite_aclk
create_bd_pin -dir I -type rst axi_lite_aresetn
create_bd_pin -dir I -type clk axis_datapath_aclk
create_bd_pin -dir I -type rst axis_datapath_aresetn
create_bd_pin -dir I -type clk sys_clk
create_bd_pin -dir I -type rst sys_reset
create_bd_pin -dir I -type clk M00_ACLK
create_bd_pin -dir I -type rst M00_ARESETN
create_bd_pin -dir I -type clk M01_ACLK
create_bd_pin -dir I -type rst M01_ARESETN
create_bd_pin -dir I -type clk M02_ACLK
create_bd_pin -dir I -type rst M02_ARESETN
create_bd_pin -dir I -type clk M03_ACLK
create_bd_pin -dir I -type rst M03_ARESETN
create_bd_pin -dir I -type clk M04_ACLK
create_bd_pin -dir I -type rst M04_ARESETN
create_bd_pin -dir I -type clk M05_ACLK
create_bd_pin -dir I -type rst M05_ARESETN
create_bd_pin -dir I -type clk M06_ACLK
create_bd_pin -dir I -type rst M06_ARESETN
create_bd_pin -dir I -type clk M07_ACLK
create_bd_pin -dir I -type rst M07_ARESETN
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list CONFIG.NUM_MI {9} ] $axi_interconnect_0
set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M08_HAS_REGSLICE {3} CONFIG.M08_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
# AXIS: clock domain crossing FIFO, TX (PCIe->FPGA) user_fifo_reset (user_clk)
set pcie_reset_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic pcie_reset_inv]
set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not}] [get_bd_cells pcie_reset_inv]
# Create instance: axis_dwidth_converter
set axis_dwidth_dma_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_tx]
set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_tx
set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {16} CONFIG.M_TDATA_NUM_BYTES {32} \
CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_tx
set axis_dwidth_dma_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_dma_rx]
set_property -dict [list CONFIG.HAS_TKEEP.VALUE_SRC USER CONFIG.HAS_TLAST.VALUE_SRC USER \
CONFIG.HAS_TSTRB.VALUE_SRC USER CONFIG.S_TDATA_NUM_BYTES.VALUE_SRC USER \
CONFIG.TUSER_BITS_PER_BYTE.VALUE_SRC USER] $axis_dwidth_dma_rx
set_property -dict [list CONFIG.S_TDATA_NUM_BYTES {32} CONFIG.M_TDATA_NUM_BYTES {16} \
CONFIG.TUSER_BITS_PER_BYTE {8} CONFIG.HAS_TLAST {1} CONFIG.HAS_TSTRB {0} \
CONFIG.HAS_TKEEP {1} CONFIG.HAS_MI_TKEEP {1}] $axis_dwidth_dma_rx
# Create instance: axis_fifo_10g_rx, and set properties
set axis_fifo_10g_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_rx]
set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_rx
# Create instance: axis_fifo_10g_tx, and set properties
set axis_fifo_10g_tx [create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_fifo_10g_tx]
set_property -dict [list CONFIG.TDATA_NUM_BYTES {16} CONFIG.TUSER_WIDTH {128} CONFIG.IS_ACLK_ASYNC {1} CONFIG.FIFO_DEPTH {32}] $axis_fifo_10g_tx
# Create instance: nf_riffa_dma_1, and set properties
set nf_riffa_dma_1 [ create_bd_cell -type ip -vlnv NetFPGA:NetFPGA:nf_riffa_dma:1.0 nf_riffa_dma_1 ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: pcie3_7x_1, and set properties
set pcie3_7x_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pcie3_7x:4.3 pcie3_7x_1 ]
set_property -dict [ list CONFIG.PF0_DEVICE_ID {7028} \
CONFIG.PF0_INTERRUPT_PIN {NONE} CONFIG.PF1_DEVICE_ID {7011} \
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {5.0_GT/s} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
CONFIG.axisten_freq {250} CONFIG.axisten_if_enable_client_tag {false} \
CONFIG.axisten_if_width {128_bit} CONFIG.cfg_ctl_if {false} \
CONFIG.cfg_ext_if {false} CONFIG.cfg_mgmt_if {false} \
CONFIG.cfg_tx_msg_if {false} CONFIG.en_ext_clk {false} \
CONFIG.extended_tag_field {true} CONFIG.gen_x0y0 {false} \
CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \
CONFIG.per_func_status_if {false} CONFIG.pf0_bar0_size {1} \
CONFIG.pf0_dev_cap_max_payload {128_bytes} CONFIG.rcv_msg_if {false} \
CONFIG.tx_fc_if {false} CONFIG.xlnx_ref_board {None} \
] $pcie3_7x_1
# Create interface connections
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_dma_rx [get_bd_intf_pins s_axis_dma_rx] [get_bd_intf_pins axis_dwidth_dma_rx/S_AXIS]
connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_rx [get_bd_intf_pins axis_fifo_10g_rx/S_AXIS] [get_bd_intf_pins axis_dwidth_dma_rx/M_AXIS]
connect_bd_intf_net -intf_net axis_fifo_10g_rx_M_AXIS [get_bd_intf_pins axis_fifo_10g_rx/M_AXIS] [get_bd_intf_pins nf_riffa_dma_1/s_axis_xge_rx]
connect_bd_intf_net -intf_net nf_riffa_dma_1_m_axis_dma_tx [get_bd_intf_pins m_axis_dma_tx] [get_bd_intf_pins axis_dwidth_dma_tx/M_AXIS]
connect_bd_intf_net -intf_net nf_riffa_dma_1_fifo_dwidth_tx [get_bd_intf_pins axis_fifo_10g_tx/M_AXIS] [get_bd_intf_pins axis_dwidth_dma_tx/S_AXIS]
connect_bd_intf_net -intf_net nf_riffa_dma_1_dwidth_conv_tx [get_bd_intf_pins axis_fifo_10g_tx/S_AXIS] [get_bd_intf_pins nf_riffa_dma_1/m_axis_xge_tx]
connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_interrupt]
connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_msi [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt_msi] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_msi]
connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_status [get_bd_intf_pins nf_riffa_dma_1/cfg] [get_bd_intf_pins pcie3_7x_1/pcie3_cfg_status]
connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie_cfg_fc [get_bd_intf_pins nf_riffa_dma_1/cfg_fc] [get_bd_intf_pins pcie3_7x_1/pcie_cfg_fc]
connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_cc [get_bd_intf_pins nf_riffa_dma_1/s_axis_cc] [get_bd_intf_pins pcie3_7x_1/s_axis_cc]
connect_bd_intf_net -intf_net nf_riffa_dma_1_s_axis_rq [get_bd_intf_pins nf_riffa_dma_1/s_axis_rq] [get_bd_intf_pins pcie3_7x_1/s_axis_rq]
connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_cq [get_bd_intf_pins nf_riffa_dma_1/m_axis_cq] [get_bd_intf_pins pcie3_7x_1/m_axis_cq]
connect_bd_intf_net -intf_net pcie3_7x_1_m_axis_rc [get_bd_intf_pins nf_riffa_dma_1/m_axis_rc] [get_bd_intf_pins pcie3_7x_1/m_axis_rc]
connect_bd_intf_net -intf_net pcie3_7x_1_pcie_7x_mgt [get_bd_intf_pins pcie_7x_mgt] [get_bd_intf_pins pcie3_7x_1/pcie_7x_mgt]
connect_bd_intf_net -intf_net s00_axi_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins nf_riffa_dma_1/m_axi_lite]
#Clock converter connections
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
set_property -dict [ list CONFIG.FREQ_HZ {250000000} ] [get_bd_intf_pins nf_riffa_dma_1/s_axi_lite]
# Create port connections
connect_bd_net -net axi_lite_clk_1 [get_bd_pins axi_lite_aclk] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aclk]
connect_bd_net -net M00_ACLK_i [get_bd_pins M00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK]
connect_bd_net -net M01_ACLK_i [get_bd_pins M01_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK]
connect_bd_net -net M02_ACLK_i [get_bd_pins M02_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK]
connect_bd_net -net M03_ACLK_i [get_bd_pins M03_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK]
connect_bd_net -net M04_ACLK_i [get_bd_pins M04_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK]
connect_bd_net -net M05_ACLK_i [get_bd_pins M05_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK]
connect_bd_net -net M06_ACLK_i [get_bd_pins M06_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK]
connect_bd_net -net M07_ACLK_i [get_bd_pins M07_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
connect_bd_net -net axi_lite_rstn_1 [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_lite_aresetn] [get_bd_pins nf_riffa_dma_1/m_axi_lite_aresetn]
connect_bd_net -net M00_ARESETN_i [get_bd_pins M00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN]
connect_bd_net -net M01_ARESETN_i [get_bd_pins M01_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN]
connect_bd_net -net M02_ARESETN_i [get_bd_pins M02_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN]
connect_bd_net -net M03_ARESETN_i [get_bd_pins M03_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN]
connect_bd_net -net M04_ARESETN_i [get_bd_pins M04_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN]
connect_bd_net -net M05_ARESETN_i [get_bd_pins M05_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN]
connect_bd_net -net M06_ARESETN_i [get_bd_pins M06_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN]
connect_bd_net -net M07_ARESETN_i [get_bd_pins M07_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
connect_bd_net -net axis_10g_clk_1 [get_bd_pins axis_datapath_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axis_dwidth_dma_rx/aclk] [get_bd_pins axis_dwidth_dma_tx/aclk] [get_bd_pins axis_fifo_10g_rx/s_axis_aclk] [get_bd_pins axis_fifo_10g_tx/m_axis_aclk]
connect_bd_net -net axis_rx_sys_reset_0_peripheral_aresetn [get_bd_pins axis_datapath_aresetn] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axis_dwidth_dma_rx/aresetn] [get_bd_pins axis_dwidth_dma_tx/aresetn] [get_bd_pins axis_fifo_10g_rx/s_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/m_axis_aresetn]
connect_bd_net -net axis_tx_sys_reset_0_peripheral_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axis_fifo_10g_rx/m_axis_aresetn] [get_bd_pins axis_fifo_10g_tx/s_axis_aresetn] [get_bd_pins pcie_reset_inv/Res]
connect_bd_net -net pcie3_7x_1_user_clk [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axis_fifo_10g_rx/m_axis_aclk] [get_bd_pins axis_fifo_10g_tx/s_axis_aclk] [get_bd_pins nf_riffa_dma_1/user_clk] [get_bd_pins pcie3_7x_1/user_clk]
connect_bd_net -net pcie3_7x_1_user_lnk_up [get_bd_pins nf_riffa_dma_1/user_lnk_up] [get_bd_pins pcie3_7x_1/user_lnk_up]
connect_bd_net -net pcie3_7x_1_user_reset [get_bd_pins pcie_reset_inv/Op1] [get_bd_pins nf_riffa_dma_1/user_reset] [get_bd_pins pcie3_7x_1/user_reset]
connect_bd_net -net sys_clk_1 [get_bd_pins sys_clk] [get_bd_pins pcie3_7x_1/sys_clk]
connect_bd_net -net sys_reset_1 [get_bd_pins sys_reset] [get_bd_pins pcie3_7x_1/sys_reset]
# Restore current instance
current_bd_instance $oldCurInst
}
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {12} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
set m_axis_dma_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma_tx ]
set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ]
set s_axis_dma_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma_rx ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.HAS_TREADY {1} CONFIG.HAS_TSTRB {0} CONFIG.LAYERED_METADATA {undef} CONFIG.PHASE {0.000} CONFIG.TDATA_NUM_BYTES {32} CONFIG.TDEST_WIDTH {0} CONFIG.TID_WIDTH {0} CONFIG.TUSER_WIDTH {128} ] $s_axis_dma_rx
set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
# Create ports
set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
set axi_lite_aresetn [ create_bd_port -dir I -type rst axi_lite_aresetn ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}] $axi_lite_aresetn
set axis_datapath_aclk [ create_bd_port -dir I -type clk axis_datapath_aclk ]
set axis_datapath_aresetn [ create_bd_port -dir I -type rst axis_datapath_aresetn ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $axis_datapath_aresetn
set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
set sys_clk [ create_bd_port -dir I -type clk sys_clk ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} ] $sys_clk
set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $sys_reset
# Create instance: dma_sub
create_hier_cell_dma_sub [current_bd_instance .] dma_sub
# Create instance: nf_mbsys
create_hier_cell_nf_mbsys [current_bd_instance .] nf_mbsys
# Create interface connections
connect_bd_intf_net -intf_net dma_sub_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins dma_sub/M00_AXI]
connect_bd_intf_net -intf_net dma_sub_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins dma_sub/M01_AXI]
connect_bd_intf_net -intf_net dma_sub_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins dma_sub/M02_AXI]
connect_bd_intf_net -intf_net dma_sub_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins dma_sub/M03_AXI]
connect_bd_intf_net -intf_net dma_sub_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins dma_sub/M04_AXI]
connect_bd_intf_net -intf_net dma_sub_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins dma_sub/M05_AXI]
connect_bd_intf_net -intf_net dma_sub_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins dma_sub/M06_AXI]
connect_bd_intf_net -intf_net dma_sub_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins dma_sub/M07_AXI]
connect_bd_intf_net -intf_net dma_sub_m_axis_dma_tx [get_bd_intf_ports m_axis_dma_tx] [get_bd_intf_pins dma_sub/m_axis_dma_tx]
connect_bd_intf_net -intf_net dma_sub_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins dma_sub/pcie_7x_mgt]
connect_bd_intf_net -intf_net nf_mbsys_iic_fpga [get_bd_intf_ports iic_fpga] [get_bd_intf_pins nf_mbsys/iic_fpga]
connect_bd_intf_net -intf_net nf_mbsys_uart [get_bd_intf_ports uart] [get_bd_intf_pins nf_mbsys/uart]
connect_bd_intf_net -intf_net s_axis_dma_rx_1 [get_bd_intf_ports s_axis_dma_rx] [get_bd_intf_pins dma_sub/s_axis_dma_rx]
# Create port connections
connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins dma_sub/axi_lite_aclk]
connect_bd_net -net axi_lite_aresetn_1 [get_bd_ports axi_lite_aresetn] [get_bd_pins dma_sub/axi_lite_aresetn]
connect_bd_net -net axis_datapath_aclk_1 [get_bd_ports axis_datapath_aclk] [get_bd_pins dma_sub/axis_datapath_aclk] [get_bd_pins dma_sub/M00_ACLK] [get_bd_pins dma_sub/M01_ACLK] [get_bd_pins dma_sub/M02_ACLK] [get_bd_pins dma_sub/M03_ACLK] [get_bd_pins dma_sub/M04_ACLK] [get_bd_pins dma_sub/M05_ACLK] [get_bd_pins dma_sub/M06_ACLK] [get_bd_pins dma_sub/M07_ACLK]
connect_bd_net -net axis_datapath_aresetn_1 [get_bd_ports axis_datapath_aresetn] [get_bd_pins dma_sub/axis_datapath_aresetn] [get_bd_pins dma_sub/M00_ARESETN] [get_bd_pins dma_sub/M01_ARESETN] [get_bd_pins dma_sub/M02_ARESETN] [get_bd_pins dma_sub/M03_ARESETN] [get_bd_pins dma_sub/M04_ARESETN] [get_bd_pins dma_sub/M05_ARESETN] [get_bd_pins dma_sub/M06_ARESETN] [get_bd_pins dma_sub/M07_ARESETN]
connect_bd_net -net nf_mbsys_iic_reset [get_bd_ports iic_reset] [get_bd_pins nf_mbsys/iic_reset]
connect_bd_net -net sys_clk_1 [get_bd_ports sys_clk] [get_bd_pins dma_sub/sys_clk] [get_bd_pins nf_mbsys/sysclk]
connect_bd_net -net sys_reset_1 [get_bd_ports sys_reset] [get_bd_pins dma_sub/sys_reset] [get_bd_pins nf_mbsys/reset]
# Create address segments
source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
create_bd_addr_seg -range $M00_SIZEADDR -offset $M00_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg
create_bd_addr_seg -range $M01_SIZEADDR -offset $M01_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M01_AXI/Reg] SEG_M01_AXI_Reg
create_bd_addr_seg -range $M02_SIZEADDR -offset $M02_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M02_AXI/Reg] SEG_M02_AXI_Reg
create_bd_addr_seg -range $M03_SIZEADDR -offset $M03_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M03_AXI/Reg] SEG_M03_AXI_Reg
create_bd_addr_seg -range $M04_SIZEADDR -offset $M04_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M04_AXI/Reg] SEG_M04_AXI_Reg
create_bd_addr_seg -range $M05_SIZEADDR -offset $M05_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M05_AXI/Reg] SEG_M05_AXI_Reg
create_bd_addr_seg -range $M06_SIZEADDR -offset $M06_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M06_AXI/Reg] SEG_M06_AXI_Reg
create_bd_addr_seg -range $M07_SIZEADDR -offset $M07_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs M07_AXI/Reg] SEG_M07_AXI_Reg
create_bd_addr_seg -range $M08_SIZEADDR -offset $M08_BASEADDR [get_bd_addr_spaces dma_sub/nf_riffa_dma_1/m_axi_lite] [get_bd_addr_segs dma_sub/nf_riffa_dma_1/s_axi_lite/reg0] SEG_nf_riffa_dma_1_reg0
create_bd_addr_seg -range $MICROBLAZE_AXI_IIC_SIZEADDR -offset $MICROBLAZE_AXI_IIC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
create_bd_addr_seg -range $MICROBLAZE_UARTLITE_SIZEADDR -offset $MICROBLAZE_UARTLITE_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
create_bd_addr_seg -range $MICROBLAZE_DLMB_BRAM_SIZEADDR -offset $MICROBLAZE_DLMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
create_bd_addr_seg -range $MICROBLAZE_ILMB_BRAM_SIZEADDR -offset $MICROBLAZE_ILMB_BRAM_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Instruction] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
create_bd_addr_seg -range $MICROBLAZE_AXI_INTC_SIZEADDR -offset $MICROBLAZE_AXI_INTC_BASEADDR [get_bd_addr_spaces nf_mbsys/mbsys/microblaze_0/Data] [get_bd_addr_segs nf_mbsys/mbsys/microblaze_0_axi_intc/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""

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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
puts "ERROR: This script was created for Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
return 1
}
################################################################
# START
################################################################
# CHANGE DESIGN NAME HERE
set design_name control_sub
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
puts "INFO: Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
puts "INFO: Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
puts "INFO: Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
puts $errMsg
return $nRet
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
puts "ERROR: Unable to find parent cell <$parentCell>!"
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M00_AXI
set M01_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M01_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M01_AXI
set M02_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M02_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M02_AXI
set M03_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M03_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M03_AXI
set M04_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M04_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M04_AXI
set M05_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M05_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M05_AXI
set M06_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M06_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M06_AXI
set M07_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M07_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.PROTOCOL {AXI4LITE} ] $M07_AXI
set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {100000000} CONFIG.ID_WIDTH {0} CONFIG.MAX_BURST_LENGTH {256} CONFIG.NUM_READ_OUTSTANDING {2} CONFIG.NUM_WRITE_OUTSTANDING {2} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S00_AXI
# Create ports
set axi_lite_aclk [ create_bd_port -dir I -type clk axi_lite_aclk ]
set axi_lite_areset [ create_bd_port -dir I -type rst axi_lite_areset ]
set core_clk [ create_bd_port -dir I -type clk core_clk ]
set_property -dict [ list CONFIG.FREQ_HZ {200000000} ] $core_clk
set core_resetn [ create_bd_port -dir I -type rst core_resetn ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list CONFIG.NUM_MI {8} CONFIG.TRANSLATION_MODE {0} ] $axi_interconnect_0
set_property -dict [list CONFIG.M00_HAS_REGSLICE {3} CONFIG.M00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M01_HAS_REGSLICE {3} CONFIG.M01_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M02_HAS_REGSLICE {3} CONFIG.M02_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M03_HAS_REGSLICE {3} CONFIG.M03_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M04_HAS_REGSLICE {3} CONFIG.M04_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M05_HAS_REGSLICE {3} CONFIG.M05_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M06_HAS_REGSLICE {3} CONFIG.M06_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.M07_HAS_REGSLICE {3} CONFIG.M07_HAS_DATA_FIFO {1} ] $axi_interconnect_0
set_property -dict [list CONFIG.S00_HAS_REGSLICE {3} CONFIG.S00_HAS_DATA_FIFO {1} ] $axi_interconnect_0
# Add AXI clock converter
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0
connect_bd_intf_net [get_bd_intf_ports S00_AXI] [get_bd_intf_pins axi_clock_converter_0/S_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_clock_converter_0/M_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
# Create interface connections
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M01_AXI] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M02_AXI] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M03_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M04_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M05_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M06_AXI] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M07_AXI] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
# Create port connections
connect_bd_net -net axi_lite_aclk_1 [get_bd_ports axi_lite_aclk] [get_bd_pins axi_clock_converter_0/s_axi_aclk]
connect_bd_net -net core_clk_1 [get_bd_ports core_clk] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK]
connect_bd_net -net axi_lite_areset_1 [get_bd_ports axi_lite_areset] [get_bd_pins axi_clock_converter_0/s_axi_aresetn]
connect_bd_net -net core_resetn_1 [get_bd_ports core_resetn] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN]
# Create address segments
source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
assign_bd_address [get_bd_addr_segs {M00_AXI/Reg }]
set_property offset $M00_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
set_property range $M00_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M00_AXI_Reg}]
assign_bd_address [get_bd_addr_segs {M01_AXI/Reg }]
set_property offset $M01_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
set_property range $M01_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M01_AXI_Reg}]
assign_bd_address [get_bd_addr_segs {M02_AXI/Reg }]
set_property offset $M02_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
set_property range $M02_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M02_AXI_Reg}]
assign_bd_address [get_bd_addr_segs {M03_AXI/Reg }]
set_property offset $M03_BASEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
set_property range $M03_SIZEADDR [get_bd_addr_segs {S00_AXI/SEG_M03_AXI_Reg}]
# Restore current instance
current_bd_instance $oldCurInst
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""

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#
# Copyright (c) 2015 University of Cambridge
# Modified by Salvator Galea
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://netfpga-cic.org
#
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
set design [lindex $argv 0]
puts "\nOpening $design XPR project\n"
open_project project/$design.xpr
puts "\nOpening $design Implementation design\n"
open_run impl_1
puts "\nCopying top.sysdef\n"
file copy -force ./project/$design.runs/impl_1/top.sysdef ../sw/embedded/$design.hdf
exit

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#
# Copyright (c) 2015 Noa Zilberman, Jingyun Zhang
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# The following list include all the items that are mapped to memory segments
# The structure of each item is as follows {<Prefix name> <ID> <has registers> <library name>}
set DEF_LIST {
{MICROBLAZE_AXI_IIC 0 0 ""} \
{MICROBLAZE_UARTLITE 0 0 ""} \
{MICROBLAZE_DLMB_BRAM 0 0 ""} \
{MICROBLAZE_ILMB_BRAM 0 0 ""} \
{MICROBLAZE_AXI_INTC 0 0 ""} \
{INPUT_ARBITER 0 1 input_arbiter_v1_0_0/data/input_arbiter_regs_defines.txt} \
{OUTPUT_QUEUES 0 1 output_queues_v1_0_0/data/output_queues_regs_defines.txt} \
{OUTPUT_PORT_LOOKUP 0 1 switch_output_port_lookup_v1_0_1/data/output_port_lookup_regs_defines.txt} \
{NF_10G_INTERFACE0 0 1 nf_10ge_interface_shared_v1_0_0/data/nf_10g_interface_shared_regs_defines.txt} \
{NF_10G_INTERFACE1 1 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
{NF_10G_INTERFACE2 2 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
{NF_10G_INTERFACE3 3 1 nf_10ge_interface_v1_0_0/data/nf_10g_interface_regs_defines.txt} \
{NF_RIFFA_DMA 0 1 nf_riffa_dma_v1_0_0/data/nf_riffa_dma_regs_defines.txt} \
}
set target_path $::env(NF_DESIGN_DIR)/sw/embedded/src/
set target_file $target_path/sume_register_defines.h
######################################################
# the following function writes the license header
# into the file
######################################################
proc write_header { target_file } {
# creat a blank header file
# do a fresh rewrite in case the file already exits
file delete -force $target_file
open $target_file "w"
set h_file [open $target_file "w"]
puts $h_file "//-"
puts $h_file "// Copyright (c) 2015 University of Cambridge"
puts $h_file "// All rights reserved."
puts $h_file "//"
puts $h_file "// This software was developed by Stanford University and the University of Cambridge Computer Laboratory "
puts $h_file "// under National Science Foundation under Grant No. CNS-0855268,"
puts $h_file "// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and"
puts $h_file "// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 (\"MRC2\"), "
puts $h_file "// as part of the DARPA MRC research programme."
puts $h_file "//"
puts $h_file "// @NETFPGA_LICENSE_HEADER_START@"
puts $h_file "//"
puts $h_file "// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor"
puts $h_file "// license agreements. See the NOTICE file distributed with this work for"
puts $h_file "// additional information regarding copyright ownership. NetFPGA licenses this"
puts $h_file "// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the"
puts $h_file "// \"License\"); you may not use this file except in compliance with the"
puts $h_file "// License. You may obtain a copy of the License at:"
puts $h_file "//"
puts $h_file "// http://www.netfpga-cic.org"
puts $h_file "//"
puts $h_file "// Unless required by applicable law or agreed to in writing, Work distributed"
puts $h_file "// under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR"
puts $h_file "// CONDITIONS OF ANY KIND, either express or implied. See the License for the"
puts $h_file "// specific language governing permissions and limitations under the License."
puts $h_file "//"
puts $h_file "// @NETFPGA_LICENSE_HEADER_END@"
puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
puts $h_file "// This is an automatically generated header definitions file"
puts $h_file "/////////////////////////////////////////////////////////////////////////////////"
puts $h_file ""
close $h_file
}; # end of proc write_header
######################################################
# the following function writes all the information
# of a specific core into a file
######################################################
proc write_core {target_file prefix id has_registers lib_name} {
set h_file [open $target_file "a"]
#First, read the memory map information from the reference_project defines file
source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
set baseaddr [set $prefix\_BASEADDR]
set highaddr [set $prefix\_HIGHADDR]
set sizeaddr [set $prefix\_SIZEADDR]
puts $h_file "//######################################################"
puts $h_file "//# Definitions for $prefix"
puts $h_file "//######################################################"
puts $h_file "#define SUME_$prefix\_BASEADDR $baseaddr"
puts $h_file "#define SUME_$prefix\_HIGHADDR $highaddr"
puts $h_file "#define SUME_$prefix\_SIZEADDR $sizeaddr"
puts $h_file ""
#Second, read the registers information from the library defines file
if $has_registers {
set lib_path "$public_repo_dir/std/cores/$lib_name"
set regs_h_define_file $lib_path
set regs_h_define_file_read [open $regs_h_define_file r]
set regs_h_define_file_data [read $regs_h_define_file_read]
close $regs_h_define_file_read
set regs_h_define_file_data_line [split $regs_h_define_file_data "\n"]
foreach read_line $regs_h_define_file_data_line {
if {[regexp "#define" $read_line]} {
puts $h_file "#define SUME_[lindex $read_line 2]\_$id\_[lindex $read_line 3]\_[lindex $read_line 4] [lindex $read_line 5]"
}
}
}
puts $h_file ""
close $h_file
}; # end of proc write_core
######################################################
# the main function
######################################################
write_header $target_file
foreach lib_item $DEF_LIST {
write_core $target_file [lindex $lib_item 0] [lindex $lib_item 1] [lindex $lib_item 2] [lindex $lib_item 3]
}

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#
# Copyright (c) 2015 University of Cambridge
# All rights reserved.
#
#
# Description:
# Vivado TCL script to insert compiled elf files into the project
# and associate it with the microblaze in the system. The script generates
# bitstreams with microblaze BRAM initialized with the elf file.
# useage:
# $ vivado -source tcl/load_elf.tcl
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
set design [lindex $argv 0]
set ws "SDK_Workspace"
# open project
puts "\nOpening $design XPR project\n"
open_project project/$design.xpr
set bd_file [get_files -regexp -nocase {.*sub*.bd}]
set elf_file ../sw/embedded/$ws/$design/app/Debug/app.elf
puts "\nOpening $design BD project\n"
open_bd_design $bd_file
# insert elf if it is not inserted yet
if {[llength [get_files app.elf]]} {
puts "ELF File [get_files app.elf] is already associated"
exit
} else {
add_files -norecurse -force ${elf_file}
set_property SCOPED_TO_REF [current_bd_design] [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
set_property SCOPED_TO_CELLS nf_mbsys/mbsys/microblaze_0 [get_files -all -of_objects [get_fileset sources_1] ${elf_file}]
}
# Create bitstream with up-to-date elf files
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
write_bitstream -force ../bitfiles/$design.bit
exit

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#
# Copyright (c) 2015 Digilent Inc.
# Copyright (c) 2015 Tinghui Wang (Steve)
# All rights reserved.
#
# File:
# nf_sume_mbsys.tcl
#
# Project:
# acceptance_test
#
# Author:
# Tinghui Wang (Steve)
#
# Description:
# tcl function to create basic microblaze sub-system (mbsys) for
# embedded design projects. Default bram size is 64KB.
# useage:
# create_hier_cell_mbsys <parentCell> <nameHier> <M_AXI_LITE_No>
#
# @NETFPGA_LICENSE_HEADER_START@
#
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
set help_msg "create_bd -name <bd_name> \[-iic <true\/false>\] \[-uart <true\/false>\] \[-add_ro <ro_width>\] \[-add_rw <rw_width>\]"
proc create_bd args {
if { [llength $args] % 2 == 1 } {
error "create_bd: Wrong # args."
puts $help_msg
}
array set opts {
-name "system"
-iic false
-uart false
-add_ro {}
-add_rw {}
}
foreach {opt value} [lrange $args 0 end] {
if {![info exist opts($opt)]} {
error "create_bd: unreconized option \"$opt\""
}
if {$opt != "-add_ro" && $opt != "-add_rw"} {
set opts($opt) $value
} else {
set opts($opt) [lappend opts($opt) $value]
}
}
# Create Block Diagram
set design_name $opts(-name)
set current_bd [create_bd_design $design_name]
current_bd_design $design_name
set parentCell [get_bd_cells /]
set parentObj [get_bd_cells $parentCell]
set parentType [get_property TYPE $parentObj]
# Create Reset Ports
set reset [ create_bd_port -dir I -type rst reset ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_HIGH} ] $reset
# Create Sysclk Ports
set sysclk [ create_bd_port -dir I -type clk sysclk ]
set_property CONFIG.FREQ_HZ 100000000 $sysclk
# Create instance: mbsys
create_mbsys [current_bd_instance .] mbsys
if { $opts(-iic) } {
create_iic
}
if { $opts(-uart) } {
create_uart
}
set index 0
foreach ro_width $opts(-add_ro) {
create_gpio_ro $index $ro_width
set index [expr $index + 1]
}
set index 0
foreach rw_width $opts(-add_rw) {
create_gpio_rw $index $rw_width
set index [expr $index + 1]
}
regenerate_bd_layout
save_bd_design
close_bd_design [current_bd_design]
}
proc create_mbsys { parentCell hierName} {
# Create microblaze and apply automation
create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze microblaze_0
apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config { \
local_mem "64KB" \
ecc "None" \
cache "None" \
debug_module "Debug Only" \
axi_periph "Enabled" \
axi_intc "1" \
clk "New Clocking Wizard (100 MHz)" }\
[get_bd_cells microblaze_0]
# Configure clock wizard
set_property -dict [list\
CONFIG.PRIM_IN_FREQ.VALUE_SRC USER]\
[get_bd_cells clk_wiz_1]
set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} CONFIG.PRIM_IN_FREQ {100.000}] [get_bd_cells clk_wiz_1]
# Connect sysclk
connect_bd_net [get_bd_pins sysclk] [get_bd_pins clk_wiz_1/clk_in1]
# Connect reset
connect_bd_net [get_bd_ports reset] [get_bd_pins clk_wiz_1/reset] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in]
# Create Hierarchy
group_bd_cells $hierName\
[get_bd_cells microblaze_0_axi_intc]\
[get_bd_cells mdm_1]\
[get_bd_cells microblaze_0_xlconcat]\
[get_bd_cells microblaze_0]\
[get_bd_cells rst_clk_wiz_1_100M]\
[get_bd_cells microblaze_0_axi_periph]\
[get_bd_cells microblaze_0_local_memory]
}
proc create_iic {} {
## Create instance: axi_iic_0, and set properties
set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic axi_iic_0 ]
set_property -dict [ list CONFIG.C_GPO_WIDTH {2} CONFIG.C_SCL_INERTIAL_DELAY {5} CONFIG.C_SDA_INERTIAL_DELAY {5} ] $axi_iic_0
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_iic_0/S_AXI]
## Create and connect to external ports
set iic_fpga [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fpga ]
set iic_reset [ create_bd_port -dir O -from 1 -to 0 iic_reset ]
connect_bd_intf_net [get_bd_intf_ports iic_fpga] [get_bd_intf_pins axi_iic_0/IIC]
connect_bd_net [get_bd_ports iic_reset] [get_bd_pins axi_iic_0/gpo]
## Connect interrupts
connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins mbsys/microblaze_0_xlconcat/In0]
}
proc create_uart {} {
## Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite axi_uartlite_0 ]
set_property -dict [ list CONFIG.C_BAUDRATE {115200} ] $axi_uartlite_0
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" } [get_bd_intf_pins axi_uartlite_0/S_AXI]
## Create and connect to external ports
set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ]
connect_bd_intf_net [get_bd_intf_ports uart] [get_bd_intf_pins axi_uartlite_0/UART]
## Connect interrupts
connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins mbsys/microblaze_0_xlconcat/In1]
}
proc create_gpio_ro { index width } {
set gpio_name axi_gpio_ro_$index
## Create instance: axi_gpio_ro, and set properties
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio $gpio_name
set_property -dict [ list\
CONFIG.C_IS_DUAL 0\
CONFIG.C_ALL_INPUTS 1\
CONFIG.C_ALL_OUTPUTS 0\
CONFIG.C_GPIO_WIDTH $width ]\
[get_bd_cells $gpio_name]
apply_bd_automation -rule xilinx.com:bd_rule:axi4\
-config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" }\
[get_bd_intf_pins $gpio_name/S_AXI]
set gpio_in_$index [create_bd_port -dir I -from [expr $width - 1] -to 0 gpio_in_$index]
connect_bd_net [get_bd_pins $gpio_name/gpio_io_i] [get_bd_ports gpio_in_$index]
}
proc create_gpio_rw { index width } {
set gpio_name axi_gpio_rw_$index
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio $gpio_name
set_property -dict [ list\
CONFIG.C_IS_DUAL 0\
CONFIG.C_ALL_INPUTS 0\
CONFIG.C_ALL_OUTPUTS 1\
CONFIG.C_GPIO_WIDTH $width ]\
[get_bd_cells $gpio_name]
apply_bd_automation -rule xilinx.com:bd_rule:axi4\
-config {Master "/mbsys/microblaze_0 (Periph)" Clk "Auto" }\
[get_bd_intf_pins $gpio_name/S_AXI]
set gpio_out_$index [create_bd_port -dir O -from [expr $width - 1] -to 0 gpio_out_$index]
connect_bd_net [get_bd_pins $gpio_name/gpio_io_o] [get_bd_ports gpio_out_$index]
}

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#
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
#### Change design settings here #######
set design $::env(NF_PROJECT_NAME)
set top top
set device xc7vx690t-3-ffg1761
set proj_dir ./project
set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
set repo_dir ./ip_repo
set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
set project_constraints ./constraints/nf_sume_general.xdc
set nf_10g_constraints ./constraints/nf_sume_10g.xdc
#####################################
# Read IP Addresses and export registers
#####################################
source ./tcl/$::env(NF_PROJECT_NAME)_defines.tcl
source ./tcl/export_registers.tcl
#####################################
# set IP paths
#####################################
#####################################
# Project Settings
#####################################
create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
set_property source_mgmt_mode DisplayOnly [current_project]
set_property top ${top} [current_fileset]
puts "Creating User Datapath reference project"
#####################################
# Project Constraints
#####################################
create_fileset -constrset -quiet constraints
file copy ${public_repo_dir}/ ${repo_dir}
set_property ip_repo_paths ${repo_dir} [current_fileset]
add_files -fileset constraints -norecurse ${bit_settings}
add_files -fileset constraints -norecurse ${project_constraints}
add_files -fileset constraints -norecurse ${nf_10g_constraints}
set_property is_enabled true [get_files ${project_constraints}]
set_property is_enabled true [get_files ${bit_settings}]
set_property is_enabled true [get_files ${nf_10g_constraints}]
set_property constrset constraints [get_runs synth_1]
set_property constrset constraints [get_runs impl_1]
#####################################
# Project
#####################################
update_ip_catalog
create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
reset_target all [get_ips input_arbiter_ip]
generate_target all [get_ips input_arbiter_ip]
create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
reset_target all [get_ips sss_output_queues_ip]
generate_target all [get_ips sss_output_queues_ip]
#create the IPI Block Diagram
source ./tcl/control_sub.tcl
#source ../hw/create_ip/nf_sume_sdnet.tcl # only need this if sdnet_to_sume has fifo in wrapper
create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
reset_target all [get_ips nf_sume_sdnet_ip]
generate_target all [get_ips nf_sume_sdnet_ip]
source ./create_ip/nf_10ge_interface.tcl
create_ip -name nf_10ge_interface -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_ip
set_property generate_synth_checkpoint false [get_files nf_10g_interface_ip.xci]
reset_target all [get_ips nf_10g_interface_ip]
generate_target all [get_ips nf_10g_interface_ip]
source ./create_ip/nf_10ge_interface_shared.tcl
create_ip -name nf_10ge_interface_shared -vendor NetFPGA -library NetFPGA -module_name nf_10g_interface_shared_ip
set_property generate_synth_checkpoint false [get_files nf_10g_interface_shared_ip.xci]
reset_target all [get_ips nf_10g_interface_shared_ip]
generate_target all [get_ips nf_10g_interface_shared_ip]
#Add a clock wizard
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
reset_target all [get_ips clk_wiz_ip]
generate_target all [get_ips clk_wiz_ip]
create_ip -name proc_sys_reset -vendor xilinx.com -library ip -version 5.0 -module_name proc_sys_reset_ip
set_property -dict [list CONFIG.C_EXT_RESET_HIGH {0} CONFIG.C_AUX_RESET_HIGH {0}] [get_ips proc_sys_reset_ip]
set_property -dict [list CONFIG.C_NUM_PERP_RST {1} CONFIG.C_NUM_PERP_ARESETN {1}] [get_ips proc_sys_reset_ip]
set_property generate_synth_checkpoint false [get_files proc_sys_reset_ip.xci]
reset_target all [get_ips proc_sys_reset_ip]
generate_target all [get_ips proc_sys_reset_ip]
#Add ID block
create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {4096} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
reset_target all [get_ips identifier_ip]
generate_target all [get_ips identifier_ip]
read_verilog "./hdl/axi_clocking.v"
read_verilog "./hdl/nf_datapath.v"
read_verilog "./hdl/top.v"
#Setting Synthesis options
create_run -flow {Vivado Synthesis 2018} synth
#Setting Implementation options
create_run impl -parent_run synth -flow {Vivado Implementation 2018}
#set_property strategy Performance_LateBlockPlacement [get_runs impl_1]
set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
#set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AlternateFlowWithRetiming [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithHoldFix [get_runs impl_1]
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.is_enabled true [get_runs impl_1]
#set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
# The following implementation options will increase runtime, but get the best timing results
#set_property strategy Performance_Explore [get_runs impl_1]
### Solves synthesis crash in 2013.2
##set_param synth.filterSetMaxDelayWithDataPathOnly true
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
launch_runs synth
wait_on_run synth
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
exit

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#
# Copyright (c) 2015 Noa Zilberman
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
######################
#MICROBLAZE Section #
######################
# MICROBLAZE_AXI_IIC base address and size
set MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
set MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
set MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
# MICROBLAZE_UARTLITE base address and size
set MICROBLAZE_UARTLITE_BASEADDR 0x40600000
set MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
set MICROBLAZE_UARTLITE_SIZEADDR 0x10000
# MICROBLAZE_DLMB_BRAM base address and size
set MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
set MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
set MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
# MICROBLAZE_UARTLITE base address and size
set MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
set MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
set MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
# MICROBLAZE_AXI_INTC base address and size
set MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
set MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
set MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
#######################
# Segments Assignment #
#######################
#M00
set M00_BASEADDR 0x44000000
set M00_HIGHADDR 0x44000FFF
set M00_SIZEADDR 0x1000
#M01
set M01_BASEADDR 0x44010000
set M01_HIGHADDR 0x44010FFF
set M01_SIZEADDR 0x1000
#M02
set M02_BASEADDR 0x44020000
set M02_HIGHADDR 0x44020FFF
set M02_SIZEADDR 0x1000
#M03
set M03_BASEADDR 0x44030000
set M03_HIGHADDR 0x44030FFF
set M03_SIZEADDR 0x1000
#M04
set M04_BASEADDR 0x44040000
set M04_HIGHADDR 0x44040FFF
set M04_SIZEADDR 0x1000
#M05
set M05_BASEADDR 0x44050000
set M05_HIGHADDR 0x44050FFF
set M05_SIZEADDR 0x1000
#M06
set M06_BASEADDR 0x44060000
set M06_HIGHADDR 0x44060FFF
set M06_SIZEADDR 0x1000
#M07
set M07_BASEADDR 0x44070000
set M07_HIGHADDR 0x44070FFF
set M07_SIZEADDR 0x1000
#M08
set M08_BASEADDR 0x44080000
set M08_HIGHADDR 0x44080FFF
set M08_SIZEADDR 0x1000
#######################
# IP_ASSIGNMENT #
#######################
# Note that physical connectivity must match this mapping
#IDENTIFIER base address and size
set IDENTIFIER_BASEADDR $M00_BASEADDR
set IDENTIFIER_HIGHADDR $M00_HIGHADDR
set IDENTIFIER_SIZEADDR $M00_SIZEADDR
#INPUT ARBITER base address and size
set INPUT_ARBITER_BASEADDR $M01_BASEADDR
set INPUT_ARBITER_HIGHADDR $M01_HIGHADDR
set INPUT_ARBITER_SIZEADDR $M01_SIZEADDR
#OUTPUT_QUEUES base address and size
set OUTPUT_QUEUES_BASEADDR $M03_BASEADDR
set OUTPUT_QUEUES_HIGHADDR $M03_HIGHADDR
set OUTPUT_QUEUES_SIZEADDR $M03_SIZEADDR
#OUPUT_PORT_LOOKUP base address and size
set OUTPUT_PORT_LOOKUP_BASEADDR $M02_BASEADDR
set OUTPUT_PORT_LOOKUP_HIGHADDR $M02_HIGHADDR
set OUTPUT_PORT_LOOKUP_SIZEADDR $M02_SIZEADDR
#SFP Port 0 base address and size
set NF_10G_INTERFACE0_BASEADDR $M04_BASEADDR
set NF_10G_INTERFACE0_HIGHADDR $M04_HIGHADDR
set NF_10G_INTERFACE0_SIZEADDR $M04_SIZEADDR
#SFP Port 1 base address and size
set NF_10G_INTERFACE1_BASEADDR $M05_BASEADDR
set NF_10G_INTERFACE1_HIGHADDR $M05_HIGHADDR
set NF_10G_INTERFACE1_SIZEADDR $M05_SIZEADDR
#SFP Port 2 base address and size
set NF_10G_INTERFACE2_BASEADDR $M06_BASEADDR
set NF_10G_INTERFACE2_HIGHADDR $M06_HIGHADDR
set NF_10G_INTERFACE2_SIZEADDR $M06_SIZEADDR
#SFP Port 3 base address and size
set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
#RIFFA base address and size
set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR

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netpfga/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl Normal file
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#
# Copyright (c) 2015 Georgina Kalogeridou
# All rights reserved.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Set variables.
set design $::env(NF_PROJECT_NAME)
set top top_sim
set sim_top top_tb
set device xc7vx690t-3-ffg1761
set proj_dir ./project
set public_repo_dir $::env(SUME_FOLDER)/lib/hw/
set xilinx_repo_dir $::env(XILINX_VIVADO)/data/ip/xilinx/
set repo_dir ./ip_repo
set bit_settings $::env(CONSTRAINTS)/generic_bit.xdc
set project_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_general.xdc
set nf_10g_constraints $::env(NF_DESIGN_DIR)/hw/constraints/nf_sume_10g.xdc
set test_name [lindex $argv 0]
#####################################
# Read IP Addresses and export registers
#####################################
source $::env(NF_DESIGN_DIR)/hw/tcl/$::env(NF_PROJECT_NAME)_defines.tcl
# Build project.
create_project -name ${design} -force -dir "$::env(NF_DESIGN_DIR)/hw/${proj_dir}" -part ${device}
set_property source_mgmt_mode DisplayOnly [current_project]
set_property top ${top} [current_fileset]
puts "Creating User Datapath reference project"
create_fileset -constrset -quiet constraints
file copy ${public_repo_dir}/ ${repo_dir}
set_property ip_repo_paths ${repo_dir} [current_fileset]
add_files -fileset constraints -norecurse ${bit_settings}
add_files -fileset constraints -norecurse ${project_constraints}
add_files -fileset constraints -norecurse ${nf_10g_constraints}
set_property is_enabled true [get_files ${project_constraints}]
set_property is_enabled true [get_files ${bit_settings}]
set_property is_enabled true [get_files ${project_constraints}]
update_ip_catalog
#source ../hw/create_ip/nf_sume_sdnet.tcl # only need this if have sdnet_to_sume fifo in wrapper
create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
set_property generate_synth_checkpoint false [get_files nf_sume_sdnet_ip.xci]
reset_target all [get_ips nf_sume_sdnet_ip]
generate_target all [get_ips nf_sume_sdnet_ip]
create_ip -name input_arbiter -vendor NetFPGA -library NetFPGA -module_name input_arbiter_ip
set_property -dict [list CONFIG.C_BASEADDR $INPUT_ARBITER_BASEADDR] [get_ips input_arbiter_ip]
set_property generate_synth_checkpoint false [get_files input_arbiter_ip.xci]
reset_target all [get_ips input_arbiter_ip]
generate_target all [get_ips input_arbiter_ip]
create_ip -name sss_output_queues -vendor NetFPGA -library NetFPGA -module_name sss_output_queues_ip
set_property -dict [list CONFIG.C_BASEADDR $OUTPUT_QUEUES_BASEADDR] [get_ips sss_output_queues_ip]
set_property generate_synth_checkpoint false [get_files sss_output_queues_ip.xci]
reset_target all [get_ips sss_output_queues_ip]
generate_target all [get_ips sss_output_queues_ip]
#Add ID block
create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name identifier_ip
set_property -dict [list CONFIG.Interface_Type {AXI4} CONFIG.AXI_Type {AXI4_Lite} CONFIG.AXI_Slave_Type {Memory_Slave} CONFIG.Use_AXI_ID {false} CONFIG.Load_Init_File {true} CONFIG.Coe_File {/../../../../../../create_ip/id_rom16x32.coe} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Remaining_Memory_Locations {DEADDEAD} CONFIG.Memory_Type {Simple_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Assume_Synchronous_Clk {true} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Read_Width_A {32} CONFIG.Operating_Mode_A {READ_FIRST} CONFIG.Write_Width_B {32} CONFIG.Read_Width_B {32} CONFIG.Operating_Mode_B {READ_FIRST} CONFIG.Enable_B {Use_ENB_Pin} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Use_RSTB_Pin {true} CONFIG.Reset_Type {ASYNC} CONFIG.Port_A_Write_Rate {50} CONFIG.Port_B_Clock {100} CONFIG.Port_B_Enable_Rate {100}] [get_ips identifier_ip]
set_property generate_synth_checkpoint false [get_files identifier_ip.xci]
reset_target all [get_ips identifier_ip]
generate_target all [get_ips identifier_ip]
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_ip
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.00} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} CONFIG.USE_SAFE_CLOCK_STARTUP {true} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.CLKOUT1_DRIVES {BUFGCE} CONFIG.CLKOUT2_DRIVES {BUFGCE} CONFIG.CLKOUT3_DRIVES {BUFGCE} CONFIG.CLKOUT4_DRIVES {BUFGCE} CONFIG.CLKOUT5_DRIVES {BUFGCE} CONFIG.CLKOUT6_DRIVES {BUFGCE} CONFIG.CLKOUT7_DRIVES {BUFGCE} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT1_JITTER {98.146} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips clk_wiz_ip]
set_property generate_synth_checkpoint false [get_files clk_wiz_ip.xci]
reset_target all [get_ips clk_wiz_ip]
generate_target all [get_ips clk_wiz_ip]
create_ip -name barrier -vendor NetFPGA -library NetFPGA -module_name barrier_ip
reset_target all [get_ips barrier_ip]
generate_target all [get_ips barrier_ip]
create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip0
set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_0_log.axi] [get_ips axis_sim_record_ip0]
reset_target all [get_ips axis_sim_record_ip0]
generate_target all [get_ips axis_sim_record_ip0]
create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip1
set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_1_log.axi] [get_ips axis_sim_record_ip1]
reset_target all [get_ips axis_sim_record_ip1]
generate_target all [get_ips axis_sim_record_ip1]
create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip2
set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_2_log.axi] [get_ips axis_sim_record_ip2]
reset_target all [get_ips axis_sim_record_ip2]
generate_target all [get_ips axis_sim_record_ip2]
create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip3
set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/nf_interface_3_log.axi] [get_ips axis_sim_record_ip3]
reset_target all [get_ips axis_sim_record_ip3]
generate_target all [get_ips axis_sim_record_ip3]
create_ip -name axis_sim_record -vendor NetFPGA -library NetFPGA -module_name axis_sim_record_ip4
set_property -dict [list CONFIG.OUTPUT_FILE $::env(NF_DESIGN_DIR)/test/dma_0_log.axi] [get_ips axis_sim_record_ip4]
reset_target all [get_ips axis_sim_record_ip4]
generate_target all [get_ips axis_sim_record_ip4]
create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip0
set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_0_stim.axi] [get_ips axis_sim_stim_ip0]
generate_target all [get_ips axis_sim_stim_ip0]
create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip1
set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_1_stim.axi] [get_ips axis_sim_stim_ip1]
generate_target all [get_ips axis_sim_stim_ip1]
create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip2
set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_2_stim.axi] [get_ips axis_sim_stim_ip2]
generate_target all [get_ips axis_sim_stim_ip2]
create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip3
set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/nf_interface_3_stim.axi] [get_ips axis_sim_stim_ip3]
generate_target all [get_ips axis_sim_stim_ip3]
create_ip -name axis_sim_stim -vendor NetFPGA -library NetFPGA -module_name axis_sim_stim_ip4
set_property -dict [list CONFIG.input_file $::env(NF_DESIGN_DIR)/test/dma_0_stim.axi] [get_ips axis_sim_stim_ip4]
generate_target all [get_ips axis_sim_stim_ip4]
create_ip -name axi_sim_transactor -vendor NetFPGA -library NetFPGA -module_name axi_sim_transactor_ip
set_property -dict [list CONFIG.STIM_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.axi CONFIG.EXPECT_FILE $::env(NF_DESIGN_DIR)/test/reg_expect.axi CONFIG.LOG_FILE $::env(NF_DESIGN_DIR)/test/reg_stim.log] [get_ips axi_sim_transactor_ip]
reset_target all [get_ips axi_sim_transactor_ip]
generate_target all [get_ips axi_sim_transactor_ip]
update_ip_catalog
source $::env(NF_DESIGN_DIR)/hw/tcl/control_sub_sim.tcl
read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/axi_clocking.v"
read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/nf_datapath.v"
read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_sim.v"
read_verilog "$::env(NF_DESIGN_DIR)/hw/hdl/top_tb.v"
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
set_property top ${sim_top} [get_filesets sim_1]
set_property include_dirs ${proj_dir} [get_filesets sim_1]
set_property simulator_language Mixed [current_project]
set_property verilog_define { {SIMULATION=1} } [get_filesets sim_1]
set_property -name xsim.more_options -value {-testplusarg TESTNAME=basic_test} -objects [get_filesets sim_1]
set_property runtime {} [get_filesets sim_1]
set_property target_simulator xsim [current_project]
set_property compxlib.xsim_compiled_library_dir {} [current_project]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]
puts $output
set_property xsim.view {} [get_filesets sim_1]
launch_simulation -simset sim_1 -mode behavioral
# Add top level datapath IO
set nf_datapath top_tb/top_sim/nf_datapath_0/
add_wave_divider {input arbiter input signals}
add_wave $nf_datapath/s_axis_0_tdata -color blue
add_wave $nf_datapath/s_axis_0_tkeep -color blue
add_wave $nf_datapath/s_axis_0_tuser -color blue
add_wave $nf_datapath/s_axis_0_tvalid -color blue
add_wave $nf_datapath/s_axis_0_tready -color blue
add_wave $nf_datapath/s_axis_0_tlast -color blue
add_wave $nf_datapath/s_axis_1_tdata -color gold
add_wave $nf_datapath/s_axis_1_tkeep -color gold
add_wave $nf_datapath/s_axis_1_tuser -color gold
add_wave $nf_datapath/s_axis_1_tvalid -color gold
add_wave $nf_datapath/s_axis_1_tready -color gold
add_wave $nf_datapath/s_axis_1_tlast -color gold
add_wave $nf_datapath/s_axis_2_tdata -color orange
add_wave $nf_datapath/s_axis_2_tkeep -color orange
add_wave $nf_datapath/s_axis_2_tuser -color orange
add_wave $nf_datapath/s_axis_2_tvalid -color orange
add_wave $nf_datapath/s_axis_2_tready -color orange
add_wave $nf_datapath/s_axis_2_tlast -color orange
add_wave $nf_datapath/s_axis_3_tdata -color purple
add_wave $nf_datapath/s_axis_3_tkeep -color purple
add_wave $nf_datapath/s_axis_3_tuser -color purple
add_wave $nf_datapath/s_axis_3_tvalid -color purple
add_wave $nf_datapath/s_axis_3_tready -color purple
add_wave $nf_datapath/s_axis_3_tlast -color purple
add_wave $nf_datapath/s_axis_4_tdata -color cyan
add_wave $nf_datapath/s_axis_4_tkeep -color cyan
add_wave $nf_datapath/s_axis_4_tuser -color cyan
add_wave $nf_datapath/s_axis_4_tvalid -color cyan
add_wave $nf_datapath/s_axis_4_tready -color cyan
add_wave $nf_datapath/s_axis_4_tlast -color cyan
add_wave_divider {output queues output signals}
add_wave $nf_datapath/m_axis_0_tdata -color blue
add_wave $nf_datapath/m_axis_0_tkeep -color blue
add_wave $nf_datapath/m_axis_0_tuser -color blue
add_wave $nf_datapath/m_axis_0_tvalid -color blue
add_wave $nf_datapath/m_axis_0_tready -color blue
add_wave $nf_datapath/m_axis_0_tlast -color blue
add_wave $nf_datapath/m_axis_1_tdata -color gold
add_wave $nf_datapath/m_axis_1_tkeep -color gold
add_wave $nf_datapath/m_axis_1_tuser -color gold
add_wave $nf_datapath/m_axis_1_tvalid -color gold
add_wave $nf_datapath/m_axis_1_tready -color gold
add_wave $nf_datapath/m_axis_1_tlast -color gold
add_wave $nf_datapath/m_axis_2_tdata -color orange
add_wave $nf_datapath/m_axis_2_tkeep -color orange
add_wave $nf_datapath/m_axis_2_tuser -color orange
add_wave $nf_datapath/m_axis_2_tvalid -color orange
add_wave $nf_datapath/m_axis_2_tready -color orange
add_wave $nf_datapath/m_axis_2_tlast -color orange
add_wave $nf_datapath/m_axis_3_tdata -color purple
add_wave $nf_datapath/m_axis_3_tkeep -color purple
add_wave $nf_datapath/m_axis_3_tuser -color purple
add_wave $nf_datapath/m_axis_3_tvalid -color purple
add_wave $nf_datapath/m_axis_3_tready -color purple
add_wave $nf_datapath/m_axis_3_tlast -color purple
add_wave $nf_datapath/m_axis_4_tdata -color cyan
add_wave $nf_datapath/m_axis_4_tkeep -color cyan
add_wave $nf_datapath/m_axis_4_tuser -color cyan
add_wave $nf_datapath/m_axis_4_tvalid -color cyan
add_wave $nf_datapath/m_axis_4_tready -color cyan
add_wave $nf_datapath/m_axis_4_tlast -color cyan
## Add top level AXI Lite control signals to P4_SWITCH
#add_wave_divider {Top-Level SDNet Control Signals}
#add_wave top_tb/top_sim/M02_AXI_araddr
#add_wave top_tb/top_sim/M02_AXI_arprot
#add_wave top_tb/top_sim/M02_AXI_arready
#add_wave top_tb/top_sim/M02_AXI_arvalid
#add_wave top_tb/top_sim/M02_AXI_awaddr
#add_wave top_tb/top_sim/M02_AXI_awprot
#add_wave top_tb/top_sim/M02_AXI_awready
#add_wave top_tb/top_sim/M02_AXI_awvalid
#add_wave top_tb/top_sim/M02_AXI_bready
#add_wave top_tb/top_sim/M02_AXI_bresp
#add_wave top_tb/top_sim/M02_AXI_bvalid
#add_wave top_tb/top_sim/M02_AXI_rdata
#add_wave top_tb/top_sim/M02_AXI_rready
#add_wave top_tb/top_sim/M02_AXI_rresp
#add_wave top_tb/top_sim/M02_AXI_rvalid
#add_wave top_tb/top_sim/M02_AXI_wdata
#add_wave top_tb/top_sim/M02_AXI_wready
#add_wave top_tb/top_sim/M02_AXI_wstrb
#add_wave top_tb/top_sim/M02_AXI_wvalid
# Add SDNet Interface Signals
set sdnet_ip top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/
add_wave_divider {SDNet Control Interface}
add_wave top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/internal_rst_done -color yellow
add_wave $sdnet_ip/control_S_AXI_AWADDR
add_wave $sdnet_ip/control_S_AXI_AWVALID
add_wave $sdnet_ip/control_S_AXI_AWREADY
add_wave $sdnet_ip/control_S_AXI_WDATA
add_wave $sdnet_ip/control_S_AXI_WSTRB
add_wave $sdnet_ip/control_S_AXI_WVALID
add_wave $sdnet_ip/control_S_AXI_WREADY
add_wave $sdnet_ip/control_S_AXI_BRESP
add_wave $sdnet_ip/control_S_AXI_BVALID
add_wave $sdnet_ip/control_S_AXI_BREADY
add_wave $sdnet_ip/control_S_AXI_ARADDR
add_wave $sdnet_ip/control_S_AXI_ARVALID
add_wave $sdnet_ip/control_S_AXI_ARREADY
add_wave $sdnet_ip/control_S_AXI_RDATA
add_wave $sdnet_ip/control_S_AXI_RRESP
add_wave $sdnet_ip/control_S_AXI_RVALID
add_wave $sdnet_ip/control_S_AXI_RREADY
set nf_sume_sdnet_ip top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/
add_wave_divider {nf_sume_sdnet input interface}
add_wave $sdnet_ip/clk_lookup_rst
add_wave $sdnet_ip/clk_lookup
add_wave $nf_sume_sdnet_ip/s_axis_tdata -radix hex
add_wave $nf_sume_sdnet_ip/s_axis_tkeep -radix hex
add_wave $nf_sume_sdnet_ip/s_axis_tvalid
add_wave $nf_sume_sdnet_ip/s_axis_tready
add_wave $nf_sume_sdnet_ip/s_axis_tlast
add_wave_divider {SDNet Tuple-In}
add_wave $nf_sume_sdnet_ip/sume_tuple_in_VALID
add_wave $nf_sume_sdnet_ip/s_axis_tuser -radix hex
add_wave $nf_sume_sdnet_ip/in_pkt_len
add_wave $nf_sume_sdnet_ip/in_src_port
add_wave $nf_sume_sdnet_ip/in_dst_port
add_wave_divider {nf_sume_sdnet output interface}
add_wave $sdnet_ip/clk_lookup_rst
add_wave $sdnet_ip/clk_lookup
add_wave $nf_sume_sdnet_ip/m_axis_tdata -radix hex
add_wave $nf_sume_sdnet_ip/m_axis_tkeep -radix hex
add_wave $nf_sume_sdnet_ip/m_axis_tvalid
add_wave $nf_sume_sdnet_ip/m_axis_tready
add_wave $nf_sume_sdnet_ip/m_axis_tlast
add_wave_divider {SDNet Tuple-Out}
add_wave $nf_sume_sdnet_ip/sume_tuple_out_VALID
add_wave $nf_sume_sdnet_ip/m_axis_tuser -radix hex
add_wave $nf_sume_sdnet_ip/out_pkt_len
add_wave $nf_sume_sdnet_ip/out_src_port
add_wave $nf_sume_sdnet_ip/out_dst_port
set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
add_wave_divider {const reg extern signals}
add_wave $const_reg_ip
add_wave_divider {const cpu reg signals}
add_wave $const_reg_ip/const_cpu_regs_inst
run 60us

95
netpfga/minip4/simple_sume_switch/sw/embedded/Makefile Normal file
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#
# Copyright (c) 2015 University of Cambridge
# Modified by Salvator Galea
# All rights reserved.
#
# File:
# Makefile
#
# Project:
# reference projects
#
#
# Description:
# This makefile is used to generate and compile SDK project for reference projects.
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
# Vivado Launch Script
################################################################################
WS = SDK_Workspace
PROJ = ${NF_PROJECT_NAME}
.PHONY: distclean clean project compile download
all:
@echo ""
@echo "NetFPGA-SUME Reference Project SW Makefile"
@echo ""
@echo "make TARGETS"
@echo "------------------------------------------------------"
@echo "project: Create software project"
@echo "compile: Compile specified project"
@echo "download: Download and run specified project via xmd"
@echo ""
@echo "clean: Remove specified project"
@echo "distclean: Remove all generated projects"
@echo ""
project:
@if [ -d ./${WS} ]; then rm -rf ./${WS}; fi
mkdir ./${WS}
xsdk -batch -source ./tcl/${PROJ}_xsdk.tcl
# Compile Command needs to run twice to get sw compiled correctly in DEBUG mode
compile:
@if [ -d ./${WS} ]; then \
cp -a ./src/. ./${WS}/${PROJ}/app/src/; \
xsdk -wait -eclipseargs -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -build all -data ./${WS}/${PROJ} -vmargs -Dorg.eclipse.cdt.core.console=org.eclipse.cdt.core.systemConsole; \
xsdk -wait -eclipseargs -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -build all -data ./${WS}/${PROJ} -vmargs -Dorg.eclipse.cdt.core.console=org.eclipse.cdt.core.systemConsole; \
else \
echo "SDK_Workspace not found"; \
fi
download:
@if [ -d ./../bitfiles ]; then \
xmd -tcl ./tcl/download.tcl `find ./../bitfiles -name "*.bit"`; \
else \
echo "Bitfile folder not found"; \
fi
clean:
rm -rf ./${WS}
rm -rf *.log
rm -rf *.jou
distclean:
rm -rf `find . -name "${WS}"`
rm -rf `find . -name "*.log"`
rm -rf `find . -name "*.jou"`

678
netpfga/minip4/simple_sume_switch/sw/embedded/reg_defines.h Normal file
View file

@ -0,0 +1,678 @@
//-
// Copyright (c) 2015 University of Cambridge
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
/////////////////////////////////////////////////////////////////////////////////
// This is an automatically generated header definitions file
/////////////////////////////////////////////////////////////////////////////////
//######################################################
//# Definitions for MICROBLAZE_AXI_IIC
//######################################################
#define SUME_MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
#define SUME_MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
#define SUME_MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_UARTLITE
//######################################################
#define SUME_MICROBLAZE_UARTLITE_BASEADDR 0x40600000
#define SUME_MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
#define SUME_MICROBLAZE_UARTLITE_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_DLMB_BRAM
//######################################################
#define SUME_MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_ILMB_BRAM
//######################################################
#define SUME_MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_AXI_INTC
//######################################################
#define SUME_MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
#define SUME_MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
#define SUME_MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
//######################################################
//# Definitions for INPUT_ARBITER
//######################################################
#define SUME_INPUT_ARBITER_BASEADDR 0x44010000
#define SUME_INPUT_ARBITER_HIGHADDR 0x44010FFF
#define SUME_INPUT_ARBITER_SIZEADDR 0x1000
#define SUME_INPUT_ARBITER_0_ID 0x44010000
#define SUME_INPUT_ARBITER_0_ID_DEFAULT 0x0000DA01
#define SUME_INPUT_ARBITER_0_ID_WIDTH 32
#define SUME_INPUT_ARBITER_0_VERSION 0x44010004
#define SUME_INPUT_ARBITER_0_VERSION_DEFAULT 0x1
#define SUME_INPUT_ARBITER_0_VERSION_WIDTH 32
#define SUME_INPUT_ARBITER_0_RESET 0x44010008
#define SUME_INPUT_ARBITER_0_RESET_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_RESET_WIDTH 16
#define SUME_INPUT_ARBITER_0_FLIP 0x4401000c
#define SUME_INPUT_ARBITER_0_FLIP_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_FLIP_WIDTH 32
#define SUME_INPUT_ARBITER_0_DEBUG 0x44010010
#define SUME_INPUT_ARBITER_0_DEBUG_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_DEBUG_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTIN 0x44010014
#define SUME_INPUT_ARBITER_0_PKTIN_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTIN_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTOUT 0x44010018
#define SUME_INPUT_ARBITER_0_PKTOUT_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTOUT_WIDTH 32
//######################################################
//# Definitions for OUTPUT_QUEUES
//######################################################
#define SUME_OUTPUT_QUEUES_BASEADDR 0x44030000
#define SUME_OUTPUT_QUEUES_HIGHADDR 0x44030FFF
#define SUME_OUTPUT_QUEUES_SIZEADDR 0x1000
#define SUME_OUTPUT_QUEUES_0_ID 0x44030000
#define SUME_OUTPUT_QUEUES_0_ID_DEFAULT 0x0000DA03
#define SUME_OUTPUT_QUEUES_0_ID_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_VERSION 0x44030004
#define SUME_OUTPUT_QUEUES_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_QUEUES_0_VERSION_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_RESET 0x44030008
#define SUME_OUTPUT_QUEUES_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_RESET_WIDTH 16
#define SUME_OUTPUT_QUEUES_0_FLIP 0x4403000c
#define SUME_OUTPUT_QUEUES_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_FLIP_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_DEBUG 0x44030010
#define SUME_OUTPUT_QUEUES_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTIN 0x44030014
#define SUME_OUTPUT_QUEUES_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTOUT 0x44030018
#define SUME_OUTPUT_QUEUES_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0 0x4403001c
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0 0x44030020
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0 0x44030024
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0 0x44030028
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0 0x4403002c
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0 0x44030030
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0 0x44030034
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1 0x44030038
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1 0x4403003c
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1 0x44030040
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1 0x44030044
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1 0x44030048
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1 0x4403004c
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1 0x44030050
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2 0x44030054
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2 0x44030058
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2 0x4403005c
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2 0x44030060
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2 0x44030064
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2 0x44030068
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2 0x4403006c
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3 0x44030070
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3 0x44030074
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3 0x44030078
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3 0x4403007c
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3 0x44030080
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3 0x44030084
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3 0x44030088
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4 0x4403008c
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4 0x44030090
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4 0x44030094
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4 0x44030098
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4 0x4403009c
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4 0x440300a0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4 0x440300a4
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_WIDTH 32
//######################################################
//# Definitions for OUTPUT_PORT_LOOKUP
//######################################################
#define SUME_OUTPUT_PORT_LOOKUP_BASEADDR 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_HIGHADDR 0x44020FFF
#define SUME_OUTPUT_PORT_LOOKUP_SIZEADDR 0x1000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_DEFAULT 0x0001DA02
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION 0x44020004
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET 0x44020008
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_WIDTH 16
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP 0x4402000c
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG 0x44020010
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN 0x44020014
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT 0x44020018
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT 0x4402001c
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS 0x44020020
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE0
//######################################################
#define SUME_NF_10G_INTERFACE0_BASEADDR 0x44040000
#define SUME_NF_10G_INTERFACE0_HIGHADDR 0x44040FFF
#define SUME_NF_10G_INTERFACE0_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID 0x44040000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION 0x44040004
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET 0x44040008
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP 0x4404000c
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG 0x44040010
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID 0x44040014
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN 0x44040018
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT 0x4404001c
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR 0x44040020
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS 0x44040024
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0 0x44040028
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1 0x4404002c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2 0x44040030
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3 0x44040034
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4 0x44040038
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5 0x4404003c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6 0x44040040
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7 0x44040044
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8 0x44040048
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9 0x4404004c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10 0x44040050
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11 0x44040054
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12 0x44040058
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13 0x4404005c
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE1
//######################################################
#define SUME_NF_10G_INTERFACE1_BASEADDR 0x44050000
#define SUME_NF_10G_INTERFACE1_HIGHADDR 0x44050FFF
#define SUME_NF_10G_INTERFACE1_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_1_ID 0x44050000
#define SUME_NF_10G_INTERFACE_1_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_1_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_VERSION 0x44050004
#define SUME_NF_10G_INTERFACE_1_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_1_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_RESET 0x44050008
#define SUME_NF_10G_INTERFACE_1_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_1_FLIP 0x4405000c
#define SUME_NF_10G_INTERFACE_1_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_DEBUG 0x44050010
#define SUME_NF_10G_INTERFACE_1_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_INTERFACEID 0x44050014
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTIN 0x44050018
#define SUME_NF_10G_INTERFACE_1_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTOUT 0x4405001c
#define SUME_NF_10G_INTERFACE_1_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR 0x44050020
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS 0x44050024
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0 0x44050028
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1 0x4405002c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2 0x44050030
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3 0x44050034
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4 0x44050038
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5 0x4405003c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6 0x44050040
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7 0x44050044
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8 0x44050048
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9 0x4405004c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10 0x44050050
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11 0x44050054
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12 0x44050058
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13 0x4405005c
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE2
//######################################################
#define SUME_NF_10G_INTERFACE2_BASEADDR 0x44060000
#define SUME_NF_10G_INTERFACE2_HIGHADDR 0x44060FFF
#define SUME_NF_10G_INTERFACE2_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_2_ID 0x44060000
#define SUME_NF_10G_INTERFACE_2_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_2_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_VERSION 0x44060004
#define SUME_NF_10G_INTERFACE_2_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_2_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_RESET 0x44060008
#define SUME_NF_10G_INTERFACE_2_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_2_FLIP 0x4406000c
#define SUME_NF_10G_INTERFACE_2_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_DEBUG 0x44060010
#define SUME_NF_10G_INTERFACE_2_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_INTERFACEID 0x44060014
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTIN 0x44060018
#define SUME_NF_10G_INTERFACE_2_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTOUT 0x4406001c
#define SUME_NF_10G_INTERFACE_2_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR 0x44060020
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS 0x44060024
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0 0x44060028
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1 0x4406002c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2 0x44060030
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3 0x44060034
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4 0x44060038
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5 0x4406003c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6 0x44060040
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7 0x44060044
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8 0x44060048
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9 0x4406004c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10 0x44060050
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11 0x44060054
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12 0x44060058
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13 0x4406005c
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE3
//######################################################
#define SUME_NF_10G_INTERFACE3_BASEADDR 0x44070000
#define SUME_NF_10G_INTERFACE3_HIGHADDR 0x44070FFF
#define SUME_NF_10G_INTERFACE3_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_3_ID 0x44070000
#define SUME_NF_10G_INTERFACE_3_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_3_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_VERSION 0x44070004
#define SUME_NF_10G_INTERFACE_3_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_3_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_RESET 0x44070008
#define SUME_NF_10G_INTERFACE_3_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_3_FLIP 0x4407000c
#define SUME_NF_10G_INTERFACE_3_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_DEBUG 0x44070010
#define SUME_NF_10G_INTERFACE_3_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_INTERFACEID 0x44070014
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTIN 0x44070018
#define SUME_NF_10G_INTERFACE_3_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTOUT 0x4407001c
#define SUME_NF_10G_INTERFACE_3_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR 0x44070020
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS 0x44070024
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0 0x44070028
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1 0x4407002c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2 0x44070030
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3 0x44070034
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4 0x44070038
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5 0x4407003c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6 0x44070040
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7 0x44070044
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8 0x44070048
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9 0x4407004c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10 0x44070050
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11 0x44070054
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12 0x44070058
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13 0x4407005c
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_RIFFA_DMA
//######################################################
#define SUME_NF_RIFFA_DMA_BASEADDR 0x44080000
#define SUME_NF_RIFFA_DMA_HIGHADDR 0x44080FFF
#define SUME_NF_RIFFA_DMA_SIZEADDR 0x1000
#define SUME_NF_RIFFA_DMA_0_ID 0x44080000
#define SUME_NF_RIFFA_DMA_0_ID_DEFAULT 0x00001FFA
#define SUME_NF_RIFFA_DMA_0_ID_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_VERSION 0x44080004
#define SUME_NF_RIFFA_DMA_0_VERSION_DEFAULT 0x1
#define SUME_NF_RIFFA_DMA_0_VERSION_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RESET 0x44080008
#define SUME_NF_RIFFA_DMA_0_RESET_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RESET_WIDTH 16
#define SUME_NF_RIFFA_DMA_0_FLIP 0x4408000c
#define SUME_NF_RIFFA_DMA_0_FLIP_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_FLIP_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_DEBUG 0x44080010
#define SUME_NF_RIFFA_DMA_0_DEBUG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_DEBUG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RQPKT 0x44080014
#define SUME_NF_RIFFA_DMA_0_RQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RCPKT 0x44080018
#define SUME_NF_RIFFA_DMA_0_RCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CQPKT 0x4408001c
#define SUME_NF_RIFFA_DMA_0_CQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CCPKT 0x44080020
#define SUME_NF_RIFFA_DMA_0_CCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGETXPKT 0x44080024
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGERXPKT 0x44080028
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIERQ 0x4408002c
#define SUME_NF_RIFFA_DMA_0_PCIERQ_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIERQ_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEPHY 0x44080030
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG 0x44080034
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2 0x44080038
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEERROR 0x4408003c
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMISC 0x44080040
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIETPH 0x44080044
#define SUME_NF_RIFFA_DMA_0_PCIETPH_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIETPH_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC1 0x44080048
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC2 0x4408004c
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC3 0x44080050
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT 0x44080054
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA 0x44080058
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT 0x4408005c
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS 0x44080060
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2 0x44080064
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2 0x44080068
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_WIDTH 32

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/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/helloworld.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Reference project main function.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include <stdio.h>
#include "platform.h"
#include "xparameters.h"
#include "string.h"
#include "xiic.h"
#include "xintc.h"
#include "xil_types.h"
#include "platform.h"
#include "mb_interface.h"
#include "xuartlite_l.h"
#define IIC_DEVICE_ID XPAR_IIC_0_DEVICE_ID
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#define IIC_INTR_ID XPAR_INTC_0_IIC_0_VEC_ID
XIic IicInstance; /* The instance of the IIC device. */
XIntc InterruptController; /* The instance of the Interrupt Controller. */
/*
* printTestResult
*
* Print "Passed/Failed" for some test category based on the auto test return value
*/
void printTestResult (char* testName, XStatus result) {
int dotLen = 40 - strlen(testName);
int i;
xil_printf("%s", testName);
for(i = 0; i < dotLen; i++) {
xil_printf(".");
}
if(result == XST_SUCCESS) {
xil_printf("Passed\r\n");
} else {
xil_printf("Failed\r\n");
}
return;
}
/*
* runAutoTest
*
* Test all the interface supported by the project automatically
*/
void runAutoTest(void) {
}
/*
* runManualTest
*
* Provide a menu for user to test each interface manually
*/
void runManualTest(void) {
xil_printf("\r\n");
while(1) {
xil_printf("---- NetFPGA-SUME Manual Test Menu ----\r\n");
xil_printf("p: Read Power Info\r\n");
xil_printf("b: Back to Main Menu\r\n");
xil_printf("Select: ");
char cmd = XUartLite_RecvByte(XPAR_UARTLITE_0_BASEADDR);
xil_printf("%c\r\n", cmd);
switch (cmd) {
case 'p':
pmReadInfo();
break;
case 'b':
return;
default:
break;
}
xil_printf("\r\n");
}
}
int main()
{
int Status;
init_platform();
xil_printf("NetFPGA-SUME SI5324 Configuration\r\n");
/*
* Setup Iic Instance
*/
Status = IicInit(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("I2C Initialization FAILED\n\r");
return XST_FAILURE;
}
/*
* Setup the Interrupt System.
*/
Status = SetupInterruptSystem(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("SetupInterruptSystem FAILED\n\r");
return XST_FAILURE;
}
/*
* Enable Iic Bus
*/
Status = IicInitPost(&IicInstance);
if (Status != XST_SUCCESS) {
xil_printf("I2C Initialization FAILED\n\r");
return XST_FAILURE;
}
config_SI5324();
while(1) {
xil_printf("============ NetFPGA-SUME ============\n\r");
xil_printf("m: Manual Test \r\n");
xil_printf("Select: ");
char cmd = XUartLite_RecvByte(XPAR_UARTLITE_0_BASEADDR);
xil_printf("%c\r\n", cmd);
switch (cmd) {
case 'm':
runManualTest();
break;
default:
break;
}
xil_printf("\r\n");
}
return 0;
}
/*****************************************************************************/
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
int SetupInterruptSystem(XIic * IicInstPtr)
{
int Status;
if (InterruptController.IsStarted == XIL_COMPONENT_IS_STARTED) {
return XST_SUCCESS;
}
/*
* Initialize the interrupt controller driver so that it's ready to use.
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XIntc_Connect(&InterruptController, IIC_INTR_ID,
(XInterruptHandler) XIic_InterruptHandler,
IicInstPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller so interrupts are enabled for all
* devices that cause interrupts.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts for the IIC device.
*/
XIntc_Enable(&InterruptController, IIC_INTR_ID);
/*
* Enable the Microblaze Interrupts.
*/
microblaze_enable_interrupts();
return XST_SUCCESS;
}

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/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_config.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Read/Write functions with timeout ability for IIC communication used by
* acceptance_test project.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xiic.h"
#include "xintc.h"
#include "xstatus.h"
#include "xil_types.h"
#include "xparameters.h"
#include "math.h"
/*
* Flags for IIC Transmit/Receive
*/
int TransmitComplete = 0;
int ReceiveComplete = 0;
extern XIic IicInstance;
/*
* Initialize Iic Structure
*/
int IicInit(XIic *IicInstPtr) {
XIic_Config *IicConfigPtr;
int Status;
/*
* Initialize the IIC device Instance.
*/
IicConfigPtr = XIic_LookupConfig(XPAR_IIC_0_DEVICE_ID);
if (IicConfigPtr == NULL) {
return XST_FAILURE;
}
/*
* Initialize Iic Instance with Config Ptr
*/
Status = XIic_CfgInitialize(IicInstPtr, IicConfigPtr, IicConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Error: XIic_Initialize FAILED\n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* Iic Send Handler
* Reset Transmit Flag to 0 after Transmit is done
*/
static void IicSendHandler(XIic *IicInstPtr) {
TransmitComplete = 0;
}
/*
* Iic Receive Handler
* Reset Receive Flag to 0 after Transmit is done
*/
static void IicRecvHandler(XIic *IicInstPtr) {
ReceiveComplete = 0;
}
/*
* Iic Status Handler
* Do nothing
*/
static void IicStatusHandler(XIic *IicInstPtr) {
return;
}
/*
* Iic Post Initialization Procedure
* Need to be called after Interrupt system is configured.
*/
int IicInitPost(XIic *IicInstPtr) {
// Setup Handlers for transmit and reception
XIic_SetSendHandler(IicInstPtr, IicInstPtr, (XIic_Handler) IicSendHandler);
XIic_SetRecvHandler(IicInstPtr, IicInstPtr, (XIic_Handler) IicRecvHandler);
XIic_SetStatusHandler(IicInstPtr, IicInstPtr, (XIic_StatusHandler) IicStatusHandler);
// Release reset on the PCA9548 IIC Switch
XIic_SetGpOutput(IicInstPtr, 0xFF);
XIic_SetGpOutput(IicInstPtr, 0x00);
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData with address added as an input parameter - Repeated Start
* *********************************************************
*/
int IicReadData(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u8 IicOptions;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
IicOptions = XIic_GetOptions(&IicInstance);
XIic_SetOptions(&IicInstance, IicOptions | XII_REPEATED_START_OPTION);
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, &addr, 1);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while((TransmitComplete) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Clear Repeated Start option
*/
XIic_SetOptions(&IicInstance, IicOptions);
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Master Recv Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData with address added as an input parameter - Stop
* *********************************************************
*/
int IicReadData2(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, &addr, 1);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Master Recv Failed with status %x\r\n", Status);
#endif
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData2: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicReadData3 with address added as an input parameter - two bytes address
* *********************************************************
*/
int IicReadData3(u8 IicAddr, u16 addr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u8 IicOptions;
u32 IicTimeoutCounter = 0;
/*
* Set Receive Flag
*/
ReceiveComplete = 1;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Start failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Set Address failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Write addr to the device
*/
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Send the Data
*/
u8 addrReorder[2];
u8 *addrPtr;
addrPtr = &addr;
addrReorder[0] = addrPtr[1];
addrReorder[1] = addrPtr[0];
Status = XIic_MasterSend(&IicInstance, addrReorder, 2);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Tx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Receive Data
*/
Status = XIic_MasterRecv(&IicInstance, BufferPtr, ByteCount);
if(Status != XST_SUCCESS) {
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Master Recv Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
}
/*
* Wait until all the data is received
*/
IicTimeoutCounter = 0;
while(((ReceiveComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter ++;
}
/*
* Handle Rx Timeout
*/
if (IicTimeoutCounter > IIC_TIMEOUT) {
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Recv Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicReadData3: IIC Stop Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*
* *********************************************************
* IicWriteData with address added as an input parameter
* *********************************************************
*/
int IicWriteData(u8 IicAddr, u8 *BufferPtr, u16 ByteCount)
{
int Status;
u32 IicTimeoutCounter = 0;
// Mark the Transmit Flag
TransmitComplete = 1;
IicInstance.Stats.TxErrors = 0;
/*
* Start Iic Device
*/
Status = XIic_Start(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Start Device Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Set Iic Address
*/
Status = XIic_SetAddress(&IicInstance, XII_ADDR_TO_SEND_TYPE, IicAddr);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Set Address Failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Send the Data
*/
Status = XIic_MasterSend(&IicInstance, BufferPtr, ByteCount);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Master Send failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
/*
* Wait till the transmission is completed
*/
while(((TransmitComplete) || (XIic_IsIicBusy(&IicInstance)==TRUE)) && IicTimeoutCounter <= IIC_TIMEOUT) {
IicTimeoutCounter++;
}
if (IicTimeoutCounter > IIC_TIMEOUT) {
TransmitComplete = 0;
XIic_Reset(&IicInstance);
Status = XIic_Stop(&IicInstance);
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Write Timeout!\r\n");
if (Status != XST_SUCCESS) {
xil_printf("IicWriteData: IIC stop failed with status %x\r\n", Status);
}
#endif
return XST_FAILURE;
}
/*
* Stop Iic Device
*/
Status = XIic_Stop(&IicInstance);
if (Status != XST_SUCCESS) {
#ifdef IIC_DEBUG
xil_printf("IicWriteData: IIC Stop failed with status %x\r\n", Status);
#endif
return XST_FAILURE;
}
return XST_SUCCESS;
}

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netpfga/minip4/simple_sume_switch/sw/embedded/src/iic_config.h Normal file
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/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_config.h
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Iic related definition used by Iic communication with NetFPGA-SUME board
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#ifndef IIC_CONFIG_H
#define IIC_CONFIG_H
#include "xil_types.h"
// PCA9548 8-port IIC Switch
#define IIC_SWITCH_ADDRESS 0x74
// Connected to IIC Buses
// Bus 0
#define IIC_BUS_SFP1 0x01
#define IIC_SFP1_ADDRESS 0x50
// Bus 1
#define IIC_BUS_SFP2 0x02
#define IIC_SFP2_ADDRESS 0x50
// Bus 2
#define IIC_BUS_SFP3 0x04
#define IIC_SFP3_ADDRESS 0x50
// Bus 3
#define IIC_BUS_SFP4 0x08
#define IIC_SFP4_ADDRESS 0x50
// Bus 4
#define IIC_BUS_DDR3 0x10
#define IIC_SI5324_ADDRESS 0x68
#define IIC_DDR3A_ADDRESS 0x01
#define IIC_DDR3B_ADDRESS 0x02
// Bus 5
#define IIC_BUS_FMC 0x20
#define IIC_FMC_CPLD 0x58
#define IIC_FMC_CDCM 0x54
#define IIC_FMC_EEPROM 0x50
// Bus 6
#define IIC_BUS_PCON 0x40
// Bus 7
#define IIC_BUS_PMOD 0x80
#define IIC_TIMEOUT 1000000UL
int IicReadData(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount);
int IicReadData2(u8 IicAddr, u8 addr, u8 *BufferPtr, u16 ByteCount);
int IicReadData3(u8 IicAddr, u16 addr, u8 *BufferPtr, u16 ByteCount);
int IicWriteData(u8 IicAddr, u8 *BufferPtr, u16 ByteCount);
#endif

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/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_pm.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* Iic codes to read power information about NetFPGA-SUME boards through
* PMBus.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xstatus.h"
#include <stdio.h>
#define PM_CMD_LOAD_PAGE 0x00
#define PM_CMD_POUT 0x96
#define PM_CMD_VOUT 0x8B
#define PM_CMD_IOUT 0x8C
struct pm_info {
char* railName;
u8 i2cAddress;
u8 pageIndex;
u16 voltage;
u16 current;
u16 power;
};
struct pm_info pm[8] = {
{
.railName = "VCC1V0",
.i2cAddress = 0x5C,
.pageIndex = 0,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC1V5",
.i2cAddress = 0x5D,
.pageIndex = 2,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC1V8",
.i2cAddress = 0x5C,
.pageIndex = 1,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC2V0",
.i2cAddress = 0x5C,
.pageIndex = 2,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "VCC3V3",
.i2cAddress = 0x5D,
.pageIndex = 1,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTAVCC",
.i2cAddress = 0x5C,
.pageIndex = 3,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTAVTT",
.i2cAddress = 0x5D,
.pageIndex = 0,
.voltage = 0,
.current = 0,
.power = 0
},{
.railName = "MGTVAUX",
.i2cAddress = 0x5D,
.pageIndex = 3,
.voltage = 0,
.current = 0,
.power = 0
}
};
/*
* This function reads the information of Power Management
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
*/
int pmReadInfo(void) {
int Status;
int i;
u8 WriteBuffer[10];
u8 ReadBuffer[30];
/*
* Write to the IIC Switch.
*/
WriteBuffer[0] = IIC_BUS_PCON; //Select Bus7 - DDR3
Status = IicWriteData(IIC_SWITCH_ADDRESS, WriteBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("pmReadInfo: PCA9548 FAILED to select PM IIC Bus\r\n");
return XST_FAILURE;
}
for(i = 0; i < 8; i++) {
int decimal;
int small;
/*
* Load Corresponding Page Info
*/
WriteBuffer[0] = PM_CMD_LOAD_PAGE;
WriteBuffer[1] = pm[i].pageIndex; //Select Bus7 - Si5326
Status = IicWriteData(pm[i].i2cAddress, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: Load Page %d Failed\r\n", pm[i].i2cAddress, pm[i].pageIndex);
return XST_FAILURE;
}
xil_printf("Power Rail %s:\r\n", pm[i].railName);
Status = IicReadData(pm[i].i2cAddress, PM_CMD_LOAD_PAGE, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
// xil_printf("Page: %d\r\n", ReadBuffer[0]);
/*
* Read Voltage
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_VOUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].voltage = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Voltage: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Voltage: 0x%x, %d V\r\n", pm[i].voltage, pm[i].voltage);
decimal = pm[i].voltage >> 13;
small = (pm[i].voltage - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tVoltage: %d.%d V\r\n", decimal, small);
/*
* Read Current
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_IOUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].current = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Current: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Current: 0x%x, %d V\r\n", pm[i].current, pm[i].current);
decimal = pm[i].current >> 13;
small = (pm[i].current - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tCurrent: %d.%d A\r\n", decimal, small);
/*
* Read Voltage
*/
Status = IicReadData(pm[i].i2cAddress, PM_CMD_POUT, ReadBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("PMBus[%x]: IIC Read Failed\r\n", pm[i].i2cAddress);
return XST_FAILURE;
}
pm[i].power = (ReadBuffer[1] << 8) + ReadBuffer[0];
// xil_printf("Power: 0x%x 0x%x V\r\n", ReadBuffer[0], ReadBuffer[1]);
// xil_printf("Power: 0x%x, %d V\r\n", pm[i].power, pm[i].power);
decimal = pm[i].power >> 13;
small = (pm[i].power - (decimal <<13)) * 1000 / (1<<13);
xil_printf("\tPower: %d.%d W\r\n", decimal, small);
}
return XST_SUCCESS;
}

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/*
* Copyright (c) 2015 Digilent Inc.
* Copyright (c) 2015 Tinghui Wang (Steve)
* All rights reserved.
*
* File:
* sw/embedded/src/iic_si5324.c
*
* Project:
* Reference project
*
* Author:
* Tinghui Wang (Steve)
*
* Description:
* IIC configuration to generate 156.25MHz clocks from SI5324
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* @NETFPGA_LICENSE_HEADER_END@
*
*/
#include "iic_config.h"
#include "xstatus.h"
#include <stdio.h>
/*
* Read register data from SI5324
*/
int read5324()
{
u32 Index;
int Status;
u8 reg_addr;
u8 ReadBuffer[20];
/*
* Read from Si5324
* Addr, Bit Field Description
* 25, N1_HS
* 31, NC1_LS
* 40, N2_HS
* 40, N2_LS
* 43, N31
*/
// for( delay = 0; delay < MAX_DELAY_COUNT; delay++);
reg_addr = 25; //N1_HS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 1; Index++) {
xil_printf("Reg %d: N1_HS = 0x%02X\r\n", reg_addr, ReadBuffer[0]);
}
reg_addr = 31; //NC1_LS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: NC1_LS = 0x%02X\r\n", reg_addr++, ReadBuffer[Index]);
}
reg_addr = 40; //N2_HS, N2_LS
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: N2_HS_LS = 0x%02X\r\n",reg_addr++, ReadBuffer[Index]);
}
reg_addr = 43; //N31
Status = IicReadData2(IIC_SI5324_ADDRESS, reg_addr, ReadBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Read Failed.\r\n");
return XST_FAILURE;
}
xil_printf("\r\n");
for (Index = 0; Index < 3; Index++) {
xil_printf("Reg %d: N31 = 0x%02X\r\n", reg_addr++, ReadBuffer[Index]);
}
return XST_SUCCESS;
}
/*
* Configure SI5324 to generate 156.25MHz
*/
int config_SI5324() {
int Status;
u8 WriteBuffer[10];
/*
* Write to the IIC Switch.
*/
WriteBuffer[0] = IIC_BUS_DDR3; //Select Bus7 - Si5326
Status = IicWriteData(IIC_SWITCH_ADDRESS, WriteBuffer, 1);
if (Status != XST_SUCCESS) {
xil_printf("PCA9548 FAILED to select Si5324 IIC Bus\r\n");
return XST_FAILURE;
}
// Set Reg 0, 1, 2, 3, 4
WriteBuffer[0] = 0;
WriteBuffer[1] = 0x54; // Reg 0: Free run, Clock always on, No Bypass (Normal Op)
WriteBuffer[2] = 0xE4; // Reg 1: CLKIN2 is second priority
WriteBuffer[3] = 0x12; // Reg 2: BWSEL set to 1
WriteBuffer[4] = 0x15; // Reg 3: CKIN1 selected, No Digital Hold, Output clocks disabled during ICAL
WriteBuffer[5] = 0x92; // Reg 4: Automatic Revertive, HIST_DEL = 0x12
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 6);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 0-4 FAILED\r\n");
return XST_FAILURE;
}
// Set Reg 10, 11
WriteBuffer[0] = 10;
WriteBuffer[1] = 0x08; // Reg 10: CKOUT2 disabled, CKOUT1 enabled
WriteBuffer[2] = 0x40; // Reg 11: CKIN1, CKIN2 enabled
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 3);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 10/11 FAILED\r\n");
return XST_FAILURE;
}
// Write Reg 25 to set N1_HS = 9
WriteBuffer[0] = 25;
WriteBuffer[1] = 0xA0;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 25 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 31,32,33 to set NC1_LS = 4
WriteBuffer[0] = 31;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x00;
WriteBuffer[3] = 0x03;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 31-33 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 40,41,42 to set N2_HS = 10, N2_LS = 150000
WriteBuffer[0] = 40;
WriteBuffer[1] = 0xC2;
WriteBuffer[2] = 0x49;
WriteBuffer[3] = 0xEF;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 40-42 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 43,44,45 to set N31 = 30475
WriteBuffer[0] = 43;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x77;
WriteBuffer[3] = 0x0B;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 43-45 FAILED\r\n");
return XST_FAILURE;
}
// Write Regs 46,47,48 to set N32 = 30475
WriteBuffer[0] = 46;
WriteBuffer[1] = 0x00;
WriteBuffer[2] = 0x77;
WriteBuffer[3] = 0x0B;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 4);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 46-48 FAILED\r\n");
return XST_FAILURE;
}
// Read Si5324 regs after update
#ifdef SI5324_DEBUG
read5324();
#endif
// Start Si5324 Internal Calibration process
// Write Reg 136 to set ICAL = 1
WriteBuffer[0] = 136;
WriteBuffer[1] = 0x40;
Status = IicWriteData(IIC_SI5324_ADDRESS, WriteBuffer, 2);
if (Status != XST_SUCCESS) {
xil_printf("SI5324 IIC Write to Reg 136 FAILED\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}

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netpfga/minip4/simple_sume_switch/sw/embedded/src/sume_register_defines.h Normal file
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//-
// Copyright (c) 2015 University of Cambridge
// All rights reserved.
//
// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
// under National Science Foundation under Grant No. CNS-0855268,
// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
// as part of the DARPA MRC research programme.
//
// @NETFPGA_LICENSE_HEADER_START@
//
// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. NetFPGA licenses this
// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.netfpga-cic.org
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @NETFPGA_LICENSE_HEADER_END@
/////////////////////////////////////////////////////////////////////////////////
// This is an automatically generated header definitions file
/////////////////////////////////////////////////////////////////////////////////
//######################################################
//# Definitions for MICROBLAZE_AXI_IIC
//######################################################
#define SUME_MICROBLAZE_AXI_IIC_BASEADDR 0x40800000
#define SUME_MICROBLAZE_AXI_IIC_HIGHADDR 0x4080FFFF
#define SUME_MICROBLAZE_AXI_IIC_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_UARTLITE
//######################################################
#define SUME_MICROBLAZE_UARTLITE_BASEADDR 0x40600000
#define SUME_MICROBLAZE_UARTLITE_HIGHADDR 0x4060FFFF
#define SUME_MICROBLAZE_UARTLITE_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_DLMB_BRAM
//######################################################
#define SUME_MICROBLAZE_DLMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_DLMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_DLMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_ILMB_BRAM
//######################################################
#define SUME_MICROBLAZE_ILMB_BRAM_BASEADDR 0x00000000
#define SUME_MICROBLAZE_ILMB_BRAM_HIGHADDR 0x0000FFFF
#define SUME_MICROBLAZE_ILMB_BRAM_SIZEADDR 0x10000
//######################################################
//# Definitions for MICROBLAZE_AXI_INTC
//######################################################
#define SUME_MICROBLAZE_AXI_INTC_BASEADDR 0x41200000
#define SUME_MICROBLAZE_AXI_INTC_HIGHADDR 0x4120FFFF
#define SUME_MICROBLAZE_AXI_INTC_SIZEADDR 0x10000
//######################################################
//# Definitions for INPUT_ARBITER
//######################################################
#define SUME_INPUT_ARBITER_BASEADDR 0x44010000
#define SUME_INPUT_ARBITER_HIGHADDR 0x44010FFF
#define SUME_INPUT_ARBITER_SIZEADDR 0x1000
#define SUME_INPUT_ARBITER_0_ID_OFFSET 0x0
#define SUME_INPUT_ARBITER_0_ID_DEFAULT 0x0000DA01
#define SUME_INPUT_ARBITER_0_ID_WIDTH 32
#define SUME_INPUT_ARBITER_0_VERSION_OFFSET 0x4
#define SUME_INPUT_ARBITER_0_VERSION_DEFAULT 0x1
#define SUME_INPUT_ARBITER_0_VERSION_WIDTH 32
#define SUME_INPUT_ARBITER_0_RESET_OFFSET 0x8
#define SUME_INPUT_ARBITER_0_RESET_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_RESET_WIDTH 16
#define SUME_INPUT_ARBITER_0_FLIP_OFFSET 0xC
#define SUME_INPUT_ARBITER_0_FLIP_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_FLIP_WIDTH 32
#define SUME_INPUT_ARBITER_0_DEBUG_OFFSET 0x10
#define SUME_INPUT_ARBITER_0_DEBUG_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_DEBUG_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTIN_OFFSET 0x14
#define SUME_INPUT_ARBITER_0_PKTIN_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTIN_WIDTH 32
#define SUME_INPUT_ARBITER_0_PKTOUT_OFFSET 0x18
#define SUME_INPUT_ARBITER_0_PKTOUT_DEFAULT 0x0
#define SUME_INPUT_ARBITER_0_PKTOUT_WIDTH 32
//######################################################
//# Definitions for OUTPUT_QUEUES
//######################################################
#define SUME_OUTPUT_QUEUES_BASEADDR 0x44030000
#define SUME_OUTPUT_QUEUES_HIGHADDR 0x44030FFF
#define SUME_OUTPUT_QUEUES_SIZEADDR 0x1000
#define SUME_OUTPUT_QUEUES_0_ID_OFFSET 0x0
#define SUME_OUTPUT_QUEUES_0_ID_DEFAULT 0x0000DA03
#define SUME_OUTPUT_QUEUES_0_ID_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_VERSION_OFFSET 0x4
#define SUME_OUTPUT_QUEUES_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_QUEUES_0_VERSION_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_RESET_OFFSET 0x8
#define SUME_OUTPUT_QUEUES_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_RESET_WIDTH 16
#define SUME_OUTPUT_QUEUES_0_FLIP_OFFSET 0xC
#define SUME_OUTPUT_QUEUES_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_FLIP_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_DEBUG_OFFSET 0x10
#define SUME_OUTPUT_QUEUES_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTIN_OFFSET 0x14
#define SUME_OUTPUT_QUEUES_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTOUT_OFFSET 0x18
#define SUME_OUTPUT_QUEUES_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_OFFSET 0x1C
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_OFFSET 0x20
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_OFFSET 0x24
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_OFFSET 0x28
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_OFFSET 0x2C
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_OFFSET 0x30
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_OFFSET 0x34
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT0_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_OFFSET 0x38
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_OFFSET 0x3C
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_OFFSET 0x40
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_OFFSET 0x44
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_OFFSET 0x48
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_OFFSET 0x4C
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_OFFSET 0x50
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT1_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_OFFSET 0x54
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_OFFSET 0x58
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_OFFSET 0x5C
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_OFFSET 0x60
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_OFFSET 0x64
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_OFFSET 0x68
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_OFFSET 0x6C
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT2_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_OFFSET 0x70
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_OFFSET 0x74
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_OFFSET 0x78
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_OFFSET 0x7C
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_OFFSET 0x80
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_OFFSET 0x84
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_OFFSET 0x88
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT3_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_OFFSET 0x8C
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_OFFSET 0x90
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESSTOREDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_OFFSET 0x94
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_OFFSET 0x98
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESREMOVEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_OFFSET 0x9C
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_OFFSET 0xA0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_BYTESDROPPEDPORT4_WIDTH 32
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_OFFSET 0xA4
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_DEFAULT 0x0
#define SUME_OUTPUT_QUEUES_0_PKTINQUEUEPORT4_WIDTH 32
//######################################################
//# Definitions for OUTPUT_PORT_LOOKUP
//######################################################
#define SUME_OUTPUT_PORT_LOOKUP_BASEADDR 0x44020000
#define SUME_OUTPUT_PORT_LOOKUP_HIGHADDR 0x44020FFF
#define SUME_OUTPUT_PORT_LOOKUP_SIZEADDR 0x1000
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_OFFSET 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_DEFAULT 0x0001DA02
#define SUME_OUTPUT_PORT_LOOKUP_0_ID_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_OFFSET 0x4
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_DEFAULT 0x1
#define SUME_OUTPUT_PORT_LOOKUP_0_VERSION_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_OFFSET 0x8
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_RESET_WIDTH 16
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_OFFSET 0xC
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_FLIP_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_OFFSET 0x10
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_DEBUG_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_OFFSET 0x14
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTIN_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_OFFSET 0x18
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_PKTOUT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_OFFSET 0x1C
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTHIT_WIDTH 32
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_OFFSET 0x20
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_DEFAULT 0x0
#define SUME_OUTPUT_PORT_LOOKUP_0_LUTMISS_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE0
//######################################################
#define SUME_NF_10G_INTERFACE0_BASEADDR 0x44040000
#define SUME_NF_10G_INTERFACE0_HIGHADDR 0x44040FFF
#define SUME_NF_10G_INTERFACE0_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_SHARED_0_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_SHARED_0_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_SHARED_0_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE1
//######################################################
#define SUME_NF_10G_INTERFACE1_BASEADDR 0x44050000
#define SUME_NF_10G_INTERFACE1_HIGHADDR 0x44050FFF
#define SUME_NF_10G_INTERFACE1_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_1_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_1_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_1_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_1_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_1_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_1_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_1_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_1_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_1_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_1_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_1_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_1_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE2
//######################################################
#define SUME_NF_10G_INTERFACE2_BASEADDR 0x44060000
#define SUME_NF_10G_INTERFACE2_HIGHADDR 0x44060FFF
#define SUME_NF_10G_INTERFACE2_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_2_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_2_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_2_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_2_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_2_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_2_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_2_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_2_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_2_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_2_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_2_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_2_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_10G_INTERFACE3
//######################################################
#define SUME_NF_10G_INTERFACE3_BASEADDR 0x44070000
#define SUME_NF_10G_INTERFACE3_HIGHADDR 0x44070FFF
#define SUME_NF_10G_INTERFACE3_SIZEADDR 0x1000
#define SUME_NF_10G_INTERFACE_3_ID_OFFSET 0x0
#define SUME_NF_10G_INTERFACE_3_ID_DEFAULT 0x00001F10
#define SUME_NF_10G_INTERFACE_3_ID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_VERSION_OFFSET 0x4
#define SUME_NF_10G_INTERFACE_3_VERSION_DEFAULT 0x1
#define SUME_NF_10G_INTERFACE_3_VERSION_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_RESET_OFFSET 0x8
#define SUME_NF_10G_INTERFACE_3_RESET_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_RESET_WIDTH 16
#define SUME_NF_10G_INTERFACE_3_FLIP_OFFSET 0xC
#define SUME_NF_10G_INTERFACE_3_FLIP_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_FLIP_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_DEBUG_OFFSET 0x10
#define SUME_NF_10G_INTERFACE_3_DEBUG_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_DEBUG_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_OFFSET 0x14
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_INTERFACEID_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTIN_OFFSET 0x18
#define SUME_NF_10G_INTERFACE_3_PKTIN_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTIN_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PKTOUT_OFFSET 0x1C
#define SUME_NF_10G_INTERFACE_3_PKTOUT_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PKTOUT_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_OFFSET 0x20
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_MACSTATUSVECTOR_WIDTH 2
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_OFFSET 0x24
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUS_WIDTH 8
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_OFFSET 0x28
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR0_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_OFFSET 0x2C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR1_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_OFFSET 0x30
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR2_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_OFFSET 0x34
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR3_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_OFFSET 0x38
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR4_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_OFFSET 0x3C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR5_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_OFFSET 0x40
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR6_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_OFFSET 0x44
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR7_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_OFFSET 0x48
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR8_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_OFFSET 0x4C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR9_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_OFFSET 0x50
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR10_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_OFFSET 0x54
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR11_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_OFFSET 0x58
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR12_WIDTH 32
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_OFFSET 0x5C
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_DEFAULT 0x0
#define SUME_NF_10G_INTERFACE_3_PCSPMASTATUSVECTOR13_WIDTH 32
//######################################################
//# Definitions for NF_RIFFA_DMA
//######################################################
#define SUME_NF_RIFFA_DMA_BASEADDR 0x44080000
#define SUME_NF_RIFFA_DMA_HIGHADDR 0x44080FFF
#define SUME_NF_RIFFA_DMA_SIZEADDR 0x1000
#define SUME_NF_RIFFA_DMA_0_ID_OFFSET 0x0
#define SUME_NF_RIFFA_DMA_0_ID_DEFAULT 0x00001FFA
#define SUME_NF_RIFFA_DMA_0_ID_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_VERSION_OFFSET 0x4
#define SUME_NF_RIFFA_DMA_0_VERSION_DEFAULT 0x1
#define SUME_NF_RIFFA_DMA_0_VERSION_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RESET_OFFSET 0x8
#define SUME_NF_RIFFA_DMA_0_RESET_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RESET_WIDTH 16
#define SUME_NF_RIFFA_DMA_0_FLIP_OFFSET 0xC
#define SUME_NF_RIFFA_DMA_0_FLIP_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_FLIP_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_DEBUG_OFFSET 0x10
#define SUME_NF_RIFFA_DMA_0_DEBUG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_DEBUG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RQPKT_OFFSET 0x14
#define SUME_NF_RIFFA_DMA_0_RQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_RCPKT_OFFSET 0x18
#define SUME_NF_RIFFA_DMA_0_RCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_RCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CQPKT_OFFSET 0x1C
#define SUME_NF_RIFFA_DMA_0_CQPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CQPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_CCPKT_OFFSET 0x20
#define SUME_NF_RIFFA_DMA_0_CCPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_CCPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_OFFSET 0x24
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGETXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_OFFSET 0x28
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_XGERXPKT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIERQ_OFFSET 0x2C
#define SUME_NF_RIFFA_DMA_0_PCIERQ_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIERQ_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_OFFSET 0x30
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEPHY_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_OFFSET 0x34
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_OFFSET 0x38
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIECONFIG2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_OFFSET 0x3C
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEERROR_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_OFFSET 0x40
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMISC_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIETPH_OFFSET 0x44
#define SUME_NF_RIFFA_DMA_0_PCIETPH_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIETPH_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_OFFSET 0x48
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC1_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_OFFSET 0x4C
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_OFFSET 0x50
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEFC3_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_OFFSET 0x54
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_OFFSET 0x58
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIDATA_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_OFFSET 0x5C
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIINT_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_OFFSET 0x60
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_OFFSET 0x64
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEMSIPENDINGSTATUS2_WIDTH 32
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_OFFSET 0x68
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_DEFAULT 0x0
#define SUME_NF_RIFFA_DMA_0_PCIEINTERRUPT2_WIDTH 32

41
netpfga/minip4/simple_sume_switch/sw/embedded/tcl/download.tcl Normal file
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#
# Copyright (c) 2015 Digilent Inc.
# Copyright (c) 2015 Tinghui Wang (Steve)
# All rights reserved.
#
# File:
# download.tcl
#
# Project:
# acceptance_test
#
# Author:
# Tinghui Wang (Steve)
#
# Description:
# Downloads the acceptance test elf
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
fpga -f [lindex $argv 0]
connect mb mdm
dow SDK_Workspace/project/Debug/project.elf
run

37
netpfga/minip4/simple_sume_switch/sw/embedded/tcl/simple_sume_switch_xsdk.tcl Normal file
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#
# Copyright (c) 2017 University of Cambridge
# Copyright (c) 2017 Salvator Galea
# All rights reserved.
#
# This software was developed by University of Cambridge Computer Laboratory
# under the ENDEAVOUR project (grant agreement 644960) as part of
# the European Union's Horizon 2020 research and innovation programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA Open Systems C.I.C. (NetFPGA) under one or more
# contributor license agreements. See the NOTICE file distributed with this
# work for additional information regarding copyright ownership. NetFPGA
# licenses this file to you under the NetFPGA Hardware-Software License,
# Version 1.0 (the License); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
set ws "SDK_Workspace"
set design $::env(NF_PROJECT_NAME)
setws ./$ws/$design
createhw -name hw_platform -hwspec ./$design.hdf
createbsp -name bsp -hwproject hw_platform -proc control_sub_i_nf_mbsys_mbsys_microblaze_0 -os standalone
createapp -name app -hwproject hw_platform -proc control_sub_i_nf_mbsys_mbsys_microblaze_0 -os standalone -lang C -app {Hello World} -bsp bsp
#importsources -name app -path ./src/
projects -build
exit

43
netpfga/minip4/simple_sume_switch/sw/embedded/xml/SDKproj.xml Normal file
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<!--
# Copyright (c) 2015 Digilent Inc.
# Copyright (c) 2015 Tinghui Wang (Steve)
# All rights reserved.
#
# File:
# SDKproj.xml
#
# Project:
# reference project
#
# Author:
# Tinghui Wang (Steve)
#
# Description:
# compiles a project
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
-->
<project name="SDK Script" default="main">
<target name="main">
<createHwProject projname="hw_platform_0" hwspecpath="hw/control_sub.xml" />
<createAppProject projname="simple_sume_switch" hwprojname="hw_platform_0" processor="nf_mbsys_mbsys_microblaze_0" bspprojname="bsp" os="standalone" template="Hello World" language="C" />
</target>
</project>

42
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#
# Copyright (c) 2015 Bjoern A. Zeeb
# All rights reserved.
#
# File:
# Makefile
#
# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
# under National Science Foundation under Grant No. CNS-0855268,
# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
# as part of the DARPA MRC research programme.
#
# @NETFPGA_LICENSE_HEADER_START@
#
# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. NetFPGA licenses this
# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at:
#
# http://www.netfpga-cic.org
#
# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# @NETFPGA_LICENSE_HEADER_END@
#
all: rwaxi
rwaxi:
cc -Wall -Werror -o rwaxi rwaxi.c \
-I../driver
clean:
rm -f rwaxi
# end

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/*
*
* Copyright (c) 2015 Bjoern A. Zeeb
* All rights reserved.
*
* File:
* rwaxi.c
*
* $Id: rwaxi.c,v 1.3 2015/06/24 22:52:20 root Exp root $
*
* Author:
* Bjoern A. Zeeb
*
* This software was developed by Stanford University and the University of Cambridge Computer Laboratory
* under National Science Foundation under Grant No. CNS-0855268,
* the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
* by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
* as part of the DARPA MRC research programme.
*
* @NETFPGA_LICENSE_HEADER_START@
*
* Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
* license agreements. See the NOTICE file distributed with this work for
* additional information regarding copyright ownership. NetFPGA licenses this
* file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
*
* http://www.netfpga-cic.org
*
* Unless required by applicable law or agreed to in writing, Work distributed
* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR