174 lines
6.1 KiB
Makefile
174 lines
6.1 KiB
Makefile
#
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# Copyright (c) 2015 Noa Zilberman, Georgina Kalogeridou
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# All rights reserved.
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#
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# File:
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# Makefile
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#
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# Description:
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# This makefile is used to generate and compile hw projects
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#
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# This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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# under National Science Foundation under Grant No. CNS-0855268,
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# the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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# by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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# as part of the DARPA MRC research programme.
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#
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# @NETFPGA_LICENSE_HEADER_START@
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#
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# Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. NetFPGA licenses this
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# file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at:
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#
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# http://www.netfpga-cic.org
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#
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# Unless required by applicable law or agreed to in writing, Work distributed
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# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# @NETFPGA_LICENSE_HEADER_END@
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#
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# Vivado Launch Script
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################################################################################
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PROJ = ${NF_PROJECT_NAME}
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all:
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@echo ""
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@echo "NetFPGA-SUME Referece Project HW Makefile"
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@echo ""
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@echo "make TARGETS"
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@echo "------------------------------------------------------"
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@echo "project: Create hardware project"
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@echo "sim: Run project simulation"
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@echo "export_to_sdk: Export implemented project to sw/embedded"
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@echo "load_elf: Load ELF file for specified project"
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@echo ""
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@echo "clean: Remove specified project"
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@echo "distclean: Remove all generated projects"
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@echo ""
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.PHONY: clean project export_to_sdk load_elf
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project: identifier
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echo "Create reference project under folder /project";\
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if test -d project/; then\
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echo "Project already exists"; \
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else \
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vivado -mode batch -source tcl/${PROJ}.tcl;\
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if [ -f patch/${PROJ}.patch ]; then\
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patch -p1 < patch/${PROJ}.patch;\
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fi;\
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fi;\
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projectgui:
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echo "Create reference project under folder /project";\
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if test -d project/; then\
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echo "Project already exists"; \
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else \
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vivado -mode gui -source tcl/${PROJ}.tcl;\
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if [ -f patch/${PROJ}.patch ]; then\
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patch -p1 < patch/${PROJ}.patch;\
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fi;\
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fi;\
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export_to_sdk: identifier
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if test -d project; then\
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echo "export ${PROJ} project to SDK"; \
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vivado -mode tcl -source tcl/export_hardware.tcl -tclargs ${PROJ};\
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else \
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echo "Project ${PROJ} does not exist.";\
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echo "Please run \"make project\" to create and build the project first";\
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fi;\
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load_elf:
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@if [ ! -d ../bitfiles ]; then mkdir ../bitfiles; fi;
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if test -d project; then\
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echo "export ${PROJ} project to SDK"; \
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vivado -mode tcl -source tcl/load_elf.tcl -tclargs ${PROJ};\
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else \
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echo "Project ${PROJ} does not exist.";\
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echo "Please run \"make project\" to create and build the project first";\
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fi;\
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identifier:
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rm -f ../hw/create_ip/id_rom16x32.coe
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cp ${SUME_FOLDER}/tools/scripts/epoch.sh . && sh epoch.sh && rm -f epoch.sh
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echo 16028002 >> rom_data.txt
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echo `${SUME_FOLDER}/run_tag.sh` >> rom_data.txt
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echo 00000204 >> rom_data.txt
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echo 0000FFFF >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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echo FFFF0000 >> rom_data.txt
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cp ${SUME_FOLDER}/tools/scripts/format_coe.py . && python format_coe.py && rm -f format_coe.py
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mv -f id_rom16x32.coe ../hw/create_ip/
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mv -f rom_data.txt ../hw/create_ip/
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sim: simclean identifier
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cp -f $(NF_DESIGN_DIR)/test/reg_defines_${NF_PROJECT_NAME}.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_${NF_PROJECT_NAME}.py
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vivado -mode batch -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
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$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
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$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
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reg:
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vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/${NF_PROJECT_NAME}_defines.tcl
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vivado -mode batch -source $(NF_DESIGN_DIR)/hw/tcl/export_registers.tcl
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cd ../sw/embedded/src && cp ${SUME_FOLDER}/tools/scripts/xparam2regdefines.py . && python xparam2regdefines.py
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cd ../sw/embedded/src && rm -f xparam2regdefines.py && mv reg_defines.h ../
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cd ../sw/embedded && cp ${SUME_FOLDER}/tools/scripts/python_parser.py . && python python_parser.py
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cd ../sw/embedded && rm -f python_parser.py && mv reg_defines.py ../../test/reg_defines_${NF_PROJECT_NAME}.py
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simgui: simclean identifier
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cp -f $(NF_DESIGN_DIR)/test/reg_defines_simple_sume_switch.py $(NF_DESIGN_DIR)/test/${TESTNAME}/reg_defines_simple_sume_switch.py
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vivado -mode gui -source ${NF_DESIGN_DIR}/hw/tcl/${NF_PROJECT_NAME}_sim.tcl -tclargs ${TESTNAME}
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$(SUME_FOLDER)/tools/scripts/nf_sim_reconcile_axi_logs.py
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$(SUME_FOLDER)/tools/scripts/nf_sim_registers_axi_logs.py
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simclean:
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rm -rf proj_* vivado*.* *.*~ .Xil* $(NF_DESIGN_DIR)/hw/ip_repo/ $(NF_DESIGN_DIR)/hw/project/
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rm -rf *[0-9]_{stim,expected,log}.axi
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rm -f *.axi
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rm -f portconfig.sim
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rm -f seed
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rm -f *.log
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rm -f ../test/Makefile
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rm -rf ../test/*.log
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rm -rf ../test/*.axi
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rm -rf ../test/seed
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rm -rf ../test/*.sim
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rm -rf ../test/proj_*
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rm -rf ../test/ip_repo
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rm -f ../test/vivado*.*
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rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.py
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rm -f ../test/*_*_*/reg_defines_${NF_PROJECT_NAME}.pyc
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distclean: clean
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clean: simclean
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rm -rfv project;\
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rm -rfv ../sw/embedded/project;\
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rm -rfv vivado*;\
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rm -rfv *.log;\
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rm -rfv .Xil;\
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rm -rfv ..rej;\
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rm -rfv .srcs;\
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rm -rfv webtalk*;\
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rm -rfv *.*~;\
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rm -rfv ip_repo;\
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rm -rfv ip_proj;\
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rm -rfv std;\
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