+log

netpfga/log/compile-2019-07-29-093902-7.1-ethertype

@@ -0,0 +1,64 @@
++ date
+Mon Jul 29 09:39:02 CEST 2019
++ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
++ make
+make -C src/ clean
+make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
+rm -f *.sdnet *.tbl .sdnet_switch_info.dat
+make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
+make -C testdata/ clean
+make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
+rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
+make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
+rm -rf nf_sume_sdnet_ip/
+rm -f 
+rm -f sw/config_tables.c
+make -C src/
+make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
+p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
+netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
+    sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
+                             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
+    sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
+                             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+netpfga_dummy.p4(20): warning: >>: shifting value with 8 bits by 11
+    sume_metadata.dst_port = (bit<8>) hdr.ethernet.ethertype >> 11;
+                             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+actions_egress.p4(51): warning: Table v6_networks is not used; removing
+table v6_networks {
+      ^^^^^^^^^^^
+actions_egress.p4(77): warning: Table v4_networks is not used; removing
+table v4_networks {
+      ^^^^^^^^^^^
+actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing
+    table nat64 {
+          ^^^^^
+actions_nat64_generic.p4(177): warning: Table nat46 is not used; removing
+    table nat46 {
+          ^^^^^
+minip4_solution.p4(19): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
+    out metadata meta,
+                 ^^^^
+minip4_solution.p4(16)
+parser RealParser(
+       ^^^^^^^^^^
+/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
+make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
+make -C testdata/
+make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
+./gen_testdata.py
+Applying pkt on nf0 at 1: 
+Applying pkt on nf1 at 2: 
+Applying pkt on nf2 at 3: 
+Applying pkt on nf3 at 4: 
+nf0_applied times:  [1]
+nf1_applied times:  [2]
+nf2_applied times:  [3]
+nf3_applied times:  [4]
+/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
+/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
+make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
+sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
+Xilinx SDNet Compiler version 2018.2, build 2342300
+