++netfpga logs
This commit is contained in:
Nico Schottelius
parent
533ae3e080
commit
4059701f63
272
doc/plan.org
272
doc/plan.org
|
|
@ -1613,39 +1613,114 @@ root@rainbow:~# apt install libncurses5-dev
|
|||
|
||||
root@rainbow:~# apt install libncurses5
|
||||
|
||||
***** DONE Run step 7: ok
|
||||
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
||||
# update_ip_catalog -rebuild
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
||||
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
||||
# ipx::infer_user_parameters [ipx::current_core]
|
||||
# ipx::check_integrity [ipx::current_core]
|
||||
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
# update_ip_catalog
|
||||
# close_project
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
|
||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
||||
[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
|
||||
***** DONE Run step 4: ok fully works now with switch_calc_headrs and gen_testdata
|
||||
****** command
|
||||
cd $P4_PROJECT_DIR && make
|
||||
****** DONE commented out the test data step to progress
|
||||
****** TODO re-enable test data cp step => data required later
|
||||
all: clean frontend compile_no_cpp_test run_scripts
|
||||
cp src/*.tbl ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||
cp testdata/*.txt ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||
cp testdata/*.axi ${SDNET_OUT_DIR}/${P4_SWITCH}/
|
||||
|
||||
# Fix introduced for SDNet 2018.2
|
||||
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
||||
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
||||
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
|
||||
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
|
||||
cp: cannot stat 'testdata/*.txt': No such file or directory
|
||||
make: *** [Makefile:17: all] Error 1
|
||||
[15:46] rainbow:minip4%
|
||||
|
||||
In testdata/Makefile:
|
||||
|
||||
all:
|
||||
echo ok
|
||||
|
||||
all2:
|
||||
./gen_testdata.py
|
||||
${SUME_SDNET}/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
||||
${SUME_SDNET}/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
|
||||
|
||||
Changing back to all:
|
||||
|
||||
make -C testdata/
|
||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
||||
./gen_testdata.py
|
||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
||||
Traceback (most recent call last):
|
||||
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 108, in <module>
|
||||
write_to_file(args.file_pcap, args.output)
|
||||
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 88, in write_to_file
|
||||
for pkt in rdpcap(file_in):
|
||||
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 728, in rdpcap
|
||||
with PcapReader(filename) as fdesc:
|
||||
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 751, in __call__
|
||||
filename, fdesc, magic = cls.open(filename)
|
||||
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 778, in open
|
||||
fdesc = open(filename, "rb")
|
||||
IOError: [Errno 2] No such file or directory: 'src.pcap'
|
||||
make[1]: *** [Makefile:5: all] Error 1
|
||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
||||
make: *** [Makefile:32: frontend] Error 2
|
||||
[15:47] rainbow:minip4%
|
||||
****** TODO debug gen_testdata.py
|
||||
***** DONE Run step 5: ok
|
||||
****** command
|
||||
#+BEGIN_EXAMPLE
|
||||
cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash
|
||||
#+END_EXAMPLE
|
||||
***** DONE Run step 6: ok => config_writes
|
||||
****** command
|
||||
#+BEGIN_CENTER
|
||||
cd $P4_PROJECT_DIR && make config_writes
|
||||
#+END_CENTER
|
||||
***** DONE Run step 7: ok - install sume library core
|
||||
****** command
|
||||
#+BEGIN_CENTER
|
||||
cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
|
||||
#+END_CENTER
|
||||
****** log
|
||||
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
||||
# update_ip_catalog -rebuild
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
||||
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
||||
# ipx::infer_user_parameters [ipx::current_core]
|
||||
# ipx::check_integrity [ipx::current_core]
|
||||
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
||||
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
||||
# ipx::save_core [ipx::current_core]
|
||||
# update_ip_catalog
|
||||
# close_project
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
|
||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
||||
[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
|
||||
|
||||
***** DONE run step 8: just copies a python script
|
||||
[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
|
||||
rm -f config_writes.py*
|
||||
rm -f *.pyc
|
||||
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
|
||||
[15:18] rainbow:sim_switch_default%
|
||||
***** TODO run step 9: sume simulation: fails with various errors, python and cp failures
|
||||
cd $SUME_FOLDER
|
||||
./tools/scripts/nf_test.py sim --major switch --minor default
|
||||
****** TODO python indent bug
|
||||
****** run command
|
||||
#+BEGIN_CENTER
|
||||
cd $NF_DESIGN_DIR/test/sim_switch_default && make
|
||||
#+END_CENTER
|
||||
****** log
|
||||
[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
|
||||
rm -f config_writes.py*
|
||||
rm -f *.pyc
|
||||
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
|
||||
[15:18] rainbow:sim_switch_default%
|
||||
***** DONE run step 9: ok sume simulation: fails with various errors, python and cp failures
|
||||
****** DONE run command
|
||||
#+BEGIN_CENTER
|
||||
cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default
|
||||
#+END_CENTER
|
||||
|
||||
****** DONE python indent bug
|
||||
# update_compile_order -fileset sim_1
|
||||
update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
|
||||
al = 21975 ; free virtual = 33161
|
||||
|
|
@ -1690,8 +1765,124 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
|
|||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
|
||||
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
||||
[15:21] rainbow:P4-NetFPGA%
|
||||
****** DONE "add_wave failed" (post python fix) -> go back to step 4
|
||||
# add_wave $nf_sume_sdnet_ip/out_src_port
|
||||
# add_wave $nf_sume_sdnet_ip/out_dst_port
|
||||
# set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
|
||||
# add_wave_divider {const reg extern signals}
|
||||
# add_wave $const_reg_ip
|
||||
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
|
||||
ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
|
||||
|
||||
**** TODO Understand which steps do what for netfpga
|
||||
while executing
|
||||
"add_wave $const_reg_ip "
|
||||
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 328)
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:31:59 2019...
|
||||
make: *** [Makefile:121: sim] Error 1
|
||||
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
|
||||
512
|
||||
=== Work directory is /tmp/nico/test/simple_sume_switch
|
||||
=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
||||
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
||||
[15:31] rainbow:P4-NetFPGA%
|
||||
***** TODO run step 10: compiling the bitstream
|
||||
****** command
|
||||
#+BEGIN_CENTER
|
||||
cd $NF_DESIGN_DIR && make
|
||||
|
||||
# or
|
||||
|
||||
cd $NF_DESIGN_DIR && make 2>&1 | tee compilelog
|
||||
|
||||
#+END_CENTER
|
||||
****** log
|
||||
Ignoring previous errors and continuing with this step => does not
|
||||
work, ends with:
|
||||
|
||||
#+BEGIN_CENTER
|
||||
Opening simple_sume_switch XPR project
|
||||
|
||||
# open_project project/$design.xpr
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
||||
# puts "\nOpening $design Implementation design\n"
|
||||
|
||||
Opening simple_sume_switch Implementation design
|
||||
|
||||
# open_run impl_1
|
||||
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
||||
Vivado%
|
||||
#+END_CENTER
|
||||
****** DONE try 2: Run 'impl_1' has not been launched. Unable to open
|
||||
#+BEGIN_CENTER
|
||||
|
||||
export simple_sume_switch project to SDK
|
||||
|
||||
****** Vivado v2018.2 (64-bit)
|
||||
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
||||
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source tcl/export_hardware.tcl
|
||||
# set design [lindex $argv 0]
|
||||
# puts "\nOpening $design XPR project\n"
|
||||
|
||||
Opening simple_sume_switch XPR project
|
||||
|
||||
# open_project project/$design.xpr
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
||||
# puts "\nOpening $design Implementation design\n"
|
||||
|
||||
Opening simple_sume_switch Implementation design
|
||||
|
||||
# open_run impl_1
|
||||
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
|
||||
Vivado%
|
||||
#+END_CENTER
|
||||
****** TODO try3: debug the REAL failing command
|
||||
******* command
|
||||
#+BEGIN_CENTER
|
||||
vivado -mode batch -source tcl/simple_sume_switch.tcl
|
||||
#+END_CENTER
|
||||
******* log
|
||||
#+BEGIN_CENTER
|
||||
ERROR: [BD 41-171] The modes of the interface pins 'cfg_interrupt'(Slave) and 'pcie3_cfg_interrupt'(Slave) are incompatible. They cannot be connected.
|
||||
ERROR: [BD 5-3] Error: running connect_bd_intf_net.
|
||||
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
|
||||
|
||||
while executing
|
||||
"connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cf..."
|
||||
(procedure "create_hier_cell_dma_sub" line 141)
|
||||
invoked from within
|
||||
"create_hier_cell_dma_sub [current_bd_instance .] dma_sub"
|
||||
(procedure "create_root_design" line 68)
|
||||
invoked from within
|
||||
"create_root_design """
|
||||
(file "./tcl/control_sub.tcl" line 729)
|
||||
|
||||
while executing
|
||||
"source ./tcl/control_sub.tcl"
|
||||
(file "tcl/simple_sume_switch.tcl" line 89)
|
||||
|
||||
#+END_CENTER
|
||||
******* TODO clarifying "simple_sume_switch.tcl"
|
||||
******** DONE What is it?
|
||||
Seems to be some kind of batch system for vivado
|
||||
******** DONE Who or what created it?
|
||||
Seems to be manually / from the project / not generated
|
||||
******** TODO Why is it incompatible?
|
||||
**** TODO Understand a bit of xilinx/netfpga/vivado
|
||||
- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
|
||||
|
||||
|
|
@ -2200,6 +2391,23 @@ INFO:main:unhandled reassambled=<Ether dst=00:00:0a:00:00:42 src=00:00:0a:00:00
|
|||
**** TODO tcp session
|
||||
**** TODO udp session
|
||||
**** TODO tcp session
|
||||
** TODO Hardware port
|
||||
*** Installation issues
|
||||
Installing vivado would stall/sleep/hang forverer due to missing
|
||||
system library, no error output.
|
||||
*** Build process
|
||||
- Very fragile, many pieces, unclear which step is required for creating
|
||||
what.
|
||||
- Fails at every step
|
||||
- Dependencies in over 80k lines of code (Makefile, python, shell)
|
||||
- Unclear error messages
|
||||
Some step did something and another step fails due do something that
|
||||
was generated by a step that is not clear what it is supposed to do
|
||||
- one step huge output, hundreds to thousands of lines, errors
|
||||
somewher in between => exceeding tmux buffers
|
||||
- non fatal/fatal errors cannot be distinguished
|
||||
grep: ../../../RELEASE_NOTES: No such file or directory
|
||||
|
||||
** TODO Comparison with existing tools (Performance, Features)
|
||||
*** Features
|
||||
| What? | Description | State in P4 | References |
|
||||
|
|
|
|||
Loading…
Reference in New Issue