++netfpga logs
This commit is contained in:
Nico Schottelius
parent
533ae3e080
commit
4059701f63
1 changed files with 240 additions and 32 deletions
272
doc/plan.org
272
doc/plan.org
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@ -1613,39 +1613,114 @@ root@rainbow:~# apt install libncurses5-dev
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root@rainbow:~# apt install libncurses5
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***** DONE Run step 7: ok
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# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
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# update_ip_catalog -rebuild
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
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WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
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# ipx::infer_user_parameters [ipx::current_core]
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# ipx::check_integrity [ipx::current_core]
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INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
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INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
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INFO: [IP_Flow 19-2187] The Product Guide file is missing.
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INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
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# ipx::save_core [ipx::current_core]
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# update_ip_catalog
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# close_project
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
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[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
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***** DONE Run step 4: ok fully works now with switch_calc_headrs and gen_testdata
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****** command
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cd $P4_PROJECT_DIR && make
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****** DONE commented out the test data step to progress
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****** TODO re-enable test data cp step => data required later
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all: clean frontend compile_no_cpp_test run_scripts
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cp src/*.tbl ${SDNET_OUT_DIR}/${P4_SWITCH}/
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cp testdata/*.txt ${SDNET_OUT_DIR}/${P4_SWITCH}/
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cp testdata/*.axi ${SDNET_OUT_DIR}/${P4_SWITCH}/
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp: cannot stat 'testdata/*.txt': No such file or directory
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make: *** [Makefile:17: all] Error 1
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[15:46] rainbow:minip4%
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In testdata/Makefile:
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all:
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echo ok
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all2:
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./gen_testdata.py
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${SUME_SDNET}/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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${SUME_SDNET}/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
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Changing back to all:
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 108, in <module>
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write_to_file(args.file_pcap, args.output)
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 88, in write_to_file
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for pkt in rdpcap(file_in):
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 728, in rdpcap
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with PcapReader(filename) as fdesc:
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 751, in __call__
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filename, fdesc, magic = cls.open(filename)
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 778, in open
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fdesc = open(filename, "rb")
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IOError: [Errno 2] No such file or directory: 'src.pcap'
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make[1]: *** [Makefile:5: all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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make: *** [Makefile:32: frontend] Error 2
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[15:47] rainbow:minip4%
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****** TODO debug gen_testdata.py
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***** DONE Run step 5: ok
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****** command
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#+BEGIN_EXAMPLE
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cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch && ./vivado_sim.bash
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#+END_EXAMPLE
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***** DONE Run step 6: ok => config_writes
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****** command
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#+BEGIN_CENTER
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cd $P4_PROJECT_DIR && make config_writes
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#+END_CENTER
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***** DONE Run step 7: ok - install sume library core
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****** command
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#+BEGIN_CENTER
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cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
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#+END_CENTER
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****** log
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# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
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# update_ip_catalog -rebuild
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
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WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
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# ipx::infer_user_parameters [ipx::current_core]
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# ipx::check_integrity [ipx::current_core]
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INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
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INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
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INFO: [IP_Flow 19-2187] The Product Guide file is missing.
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INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
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# ipx::save_core [ipx::current_core]
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# update_ip_catalog
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# close_project
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
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[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
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***** DONE run step 8: just copies a python script
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[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
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rm -f config_writes.py*
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rm -f *.pyc
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
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[15:18] rainbow:sim_switch_default%
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***** TODO run step 9: sume simulation: fails with various errors, python and cp failures
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cd $SUME_FOLDER
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./tools/scripts/nf_test.py sim --major switch --minor default
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****** TODO python indent bug
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****** run command
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#+BEGIN_CENTER
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cd $NF_DESIGN_DIR/test/sim_switch_default && make
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#+END_CENTER
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****** log
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[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
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rm -f config_writes.py*
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rm -f *.pyc
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
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[15:18] rainbow:sim_switch_default%
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***** DONE run step 9: ok sume simulation: fails with various errors, python and cp failures
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****** DONE run command
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#+BEGIN_CENTER
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cd $SUME_FOLDER && ./tools/scripts/nf_test.py sim --major switch --minor default
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#+END_CENTER
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****** DONE python indent bug
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# update_compile_order -fileset sim_1
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update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
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al = 21975 ; free virtual = 33161
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@ -1690,8 +1765,124 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
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[15:21] rainbow:P4-NetFPGA%
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****** DONE "add_wave failed" (post python fix) -> go back to step 4
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# add_wave $nf_sume_sdnet_ip/out_src_port
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# add_wave $nf_sume_sdnet_ip/out_dst_port
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# set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
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# add_wave_divider {const reg extern signals}
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# add_wave $const_reg_ip
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ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
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ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
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**** TODO Understand which steps do what for netfpga
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while executing
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"add_wave $const_reg_ip "
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 328)
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:31:59 2019...
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make: *** [Makefile:121: sim] Error 1
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
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512
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=== Work directory is /tmp/nico/test/simple_sume_switch
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=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
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[15:31] rainbow:P4-NetFPGA%
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***** TODO run step 10: compiling the bitstream
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****** command
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#+BEGIN_CENTER
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cd $NF_DESIGN_DIR && make
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# or
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cd $NF_DESIGN_DIR && make 2>&1 | tee compilelog
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#+END_CENTER
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****** log
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Ignoring previous errors and continuing with this step => does not
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work, ends with:
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#+BEGIN_CENTER
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Opening simple_sume_switch XPR project
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# open_project project/$design.xpr
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
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# puts "\nOpening $design Implementation design\n"
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Opening simple_sume_switch Implementation design
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# open_run impl_1
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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#+END_CENTER
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****** DONE try 2: Run 'impl_1' has not been launched. Unable to open
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#+BEGIN_CENTER
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export simple_sume_switch project to SDK
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****** Vivado v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source tcl/export_hardware.tcl
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# set design [lindex $argv 0]
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# puts "\nOpening $design XPR project\n"
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Opening simple_sume_switch XPR project
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# open_project project/$design.xpr
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
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# puts "\nOpening $design Implementation design\n"
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Opening simple_sume_switch Implementation design
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# open_run impl_1
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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#+END_CENTER
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****** TODO try3: debug the REAL failing command
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******* command
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#+BEGIN_CENTER
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vivado -mode batch -source tcl/simple_sume_switch.tcl
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#+END_CENTER
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******* log
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#+BEGIN_CENTER
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ERROR: [BD 41-171] The modes of the interface pins 'cfg_interrupt'(Slave) and 'pcie3_cfg_interrupt'(Slave) are incompatible. They cannot be connected.
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ERROR: [BD 5-3] Error: running connect_bd_intf_net.
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ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
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while executing
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"connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cf..."
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(procedure "create_hier_cell_dma_sub" line 141)
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invoked from within
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"create_hier_cell_dma_sub [current_bd_instance .] dma_sub"
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(procedure "create_root_design" line 68)
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invoked from within
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"create_root_design """
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(file "./tcl/control_sub.tcl" line 729)
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while executing
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"source ./tcl/control_sub.tcl"
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(file "tcl/simple_sume_switch.tcl" line 89)
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#+END_CENTER
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******* TODO clarifying "simple_sume_switch.tcl"
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******** DONE What is it?
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Seems to be some kind of batch system for vivado
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******** DONE Who or what created it?
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Seems to be manually / from the project / not generated
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******** TODO Why is it incompatible?
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**** TODO Understand a bit of xilinx/netfpga/vivado
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- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
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@ -2200,6 +2391,23 @@ INFO:main:unhandled reassambled=<Ether dst=00:00:0a:00:00:42 src=00:00:0a:00:00
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**** TODO tcp session
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**** TODO udp session
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**** TODO tcp session
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** TODO Hardware port
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*** Installation issues
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Installing vivado would stall/sleep/hang forverer due to missing
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system library, no error output.
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*** Build process
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- Very fragile, many pieces, unclear which step is required for creating
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what.
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- Fails at every step
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- Dependencies in over 80k lines of code (Makefile, python, shell)
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- Unclear error messages
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Some step did something and another step fails due do something that
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was generated by a step that is not clear what it is supposed to do
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- one step huge output, hundreds to thousands of lines, errors
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somewher in between => exceeding tmux buffers
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- non fatal/fatal errors cannot be distinguished
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grep: ../../../RELEASE_NOTES: No such file or directory
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** TODO Comparison with existing tools (Performance, Features)
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*** Features
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| What? | Description | State in P4 | References |
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