++ log netpfga
This commit is contained in:
Nico Schottelius
parent
6a3c1a6e68
commit
533ae3e080
2 changed files with 321 additions and 2 deletions
305
doc/plan.org
305
doc/plan.org
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@ -1416,12 +1416,315 @@ Please make sure that it is installed and available in your $PATH:
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*** DONE Get access to tofino: no, NDA issues
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*** TODO Get NetFPGA running
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**** TODO Understand the simulations part
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**** TODO Install vivado
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**** DONE Install vivado
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**** DONE Install SDNET
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**** TODO Create either HDL or PX for supporting payload checksum
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https://github.com/NetFPGA/P4-NetFPGA-public/issues/13
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https://github.com/NetFPGA/P4-NetFPGA-public/issues/13#issuecomment-490431016
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***** TODO Explore HDL
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***** TODO Explore PX
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**** DONE fix license issue
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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echo ok
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ok
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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sdnet ./src/switch_calc.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
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Xilinx SDNet Compiler version 2018.2, build 2342300
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Cannot obtain license
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make: *** [Makefile:67: compile_no_cpp_test] Error 1
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$
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**** TODO Testing / compiling / uploading stuff to the NetPFGA --
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https://github.com/NetFPGA/P4-NetFPGA-public/wiki/Tutorial-Assignments
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***** DONE try 1
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According to
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DO NOT USE THIS:: ==> https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-Learning-Switch
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root@loch:~/projects/P4-NetFPGA/tools/scripts# ./nf_test.py hw --major learning --minor sw
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Please set the environment variable 'SUME_FOLDER' to point to the local NetFPGA source
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Traceback (most recent call last):
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File "./nf_test.py", line 632, in <module>
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identifyWorkDir()
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File "./nf_test.py", line 418, in identifyWorkDir
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project = os.path.basename(os.path.abspath(os.environ['NF_DESIGN_DIR']))
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File "/usr/lib/python2.7/UserDict.py", line 40, in __getitem__
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raise KeyError(key)
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KeyError: 'NF_DESIGN_DIR'
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root@loch:~/projects/P4-NetFPGA/tools/scripts#
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Trying
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https://github.com/NetFPGA/P4-NetFPGA-public/wiki/Tutorial-Assignments
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src# mv switch_calc.p4 switch_calc_orig.p4
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src# ln -s switch_calc_solution.p4 switch_calc.p4
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src#
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc# make
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make -C src/ clean
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make -C testdata/ clean
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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p4c-sdnet -o .sdnet --sdnet_info .sdnet_switch_info.dat _solution.p4
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make[1]: p4c-sdnet: Command not found
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make[1]: *** [Makefile:34: all] Error 127
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make[1]: Leaving directory '/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make: *** [Makefile:60: frontend] Error 2
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root@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc#
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As nico:
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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p4c-sdnet -o switch_calc.sdnet --sdnet_info .sdnet_switch_info.dat switch_calc_solution.p4
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cpp: error: switch_calc_solution.p4: No such file or directory
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cpp: warning: ‘-x c’ after last input file has no effect
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cpp: fatal error: no input files
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compilation terminated.
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error: Preprocessor returned exit code 256; aborting compilation
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error: 1 errors encountered, aborting compilation
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make[1]: *** [Makefile:34: all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src'
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make: *** [Makefile:60: frontend] Error 2
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc$
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nico@loch:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/src$ cp switch_calc.p4 switch_calc_solution.p4
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$ cd $P4_PROJECT_DIR/nf_sume_sdnet_ip/SimpleSumeSwitch
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$ ./vivado_sim.bash.
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***** DONE try 2: create an almost empty p4 project based on switch_calc
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****** DONE frontend build: ok
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****** DONE testdata: skipped
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****** DONE compile_cpp_test: ok
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****** DONE run_scripts: ok
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****** TODO cpp_test: error
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# Fix introduced for SDNet 2017.4
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp: cannot stat 'src/*.tbl': No such file or directory
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make: *** [Makefile:23: cpp_test] Error 1
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[23:12] loch:minip4%
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******* DONE Removing cp of *tbl
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******* DONE Removing pcap copy
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******* TODO removing all cp's
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***** DONE try 3: good until step 4; broken at the simulation
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****** log 1
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[15:26] rainbow:~% echo $P4_PROJECT_DIR
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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[15:26] rainbow:~%
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[15:26] rainbow:~% cd $P4_PROJECT_DIR && make
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.S_SYNCER_for_S_SYNCER_for_TopDep...
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.S_SYNCER_for_TopDeparser
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
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Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.S_SYNCER_for__OUT_
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Compiling module work.S_CONTROLLER_SimpleSumeSwitch
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Compiling module work.SimpleSumeSwitch
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Compiling module work.TB_System_Stim
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Compiling module work.Check
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Compiling module work.SimpleSumeSwitch_tb
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Compiling module work.glbl
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ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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[15:29] rainbow:SimpleSumeSwitch% ./vivado_sim.bash
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****** trying to find the error in the generated c code
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[15:29] rainbow:SimpleSumeSwitch% find . -name xsim_3.c
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./xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c
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****** error seems to occur in xelab
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***** DONE try 4: vivado 2018.2 instead of 2018.3
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Probably both ok - errors are the same
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***** DONE new error: /usr/include/stdio.h:27:36: fatal error: bits/libc-header-start.h: No such file or directory
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apt-get install gcc-multilib g++-multilib
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***** DONE same error
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Compiling module work.glbl
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ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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[17:47] rainbow:SimpleSumeSwitch%
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***** DONE with verbosity / fixing ncurses dependency
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ICR Memory Usage: 5072KB, 18432KB
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/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang -fPIC -c -std=gnu89 -nobuiltininc -nostdinc++ -w -Wl,--unres
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olved-symbols=ignore-in-object-files -fbracket-depth=1048576 -I/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/../li
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b/clang/3.1/include -fPIC -m64 -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/ob
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j/xsim_3.c" -O0 -sim -o "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.lnx64.o" -DXILINX_SIMULATOR
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/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot
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open shared object file: No such file or directory
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ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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[20:00] rainbow:SimpleSumeSwitch%
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root@rainbow:~# apt install libncurses5-dev
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[20:02] rainbow:~% ldd /opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang
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linux-vdso.so.1 (0x00007ffda6bf6000)
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libz.so.1 => /lib/x86_64-linux-gnu/libz.so.1 (0x00007f8e23208000)
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libpthread.so.0 => /lib/x86_64-linux-gnu/libpthread.so.0 (0x00007f8e231e7000)
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libncurses.so.5 => not found
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librt.so.1 => /lib/x86_64-linux-gnu/librt.so.1 (0x00007f8e231dc000)
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libdl.so.2 => /lib/x86_64-linux-gnu/libdl.so.2 (0x00007f8e231d6000)
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libstdc++.so.6 => /lib/x86_64-linux-gnu/libstdc++.so.6 (0x00007f8e22ff5000)
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libm.so.6 => /lib/x86_64-linux-gnu/libm.so.6 (0x00007f8e22ea5000)
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libgcc_s.so.1 => /lib/x86_64-linux-gnu/libgcc_s.so.1 (0x00007f8e22e8b000)
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libc.so.6 => /lib/x86_64-linux-gnu/libc.so.6 (0x00007f8e22ca0000)
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/lib64/ld-linux-x86-64.so.2 (0x00007f8e2323f000)
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[20:02] rainbow:~%
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root@rainbow:~# apt install libncurses5
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***** DONE Run step 7: ok
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# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
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# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
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# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
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# update_ip_catalog -rebuild
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
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WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
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# ipx::infer_user_parameters [ipx::current_core]
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# ipx::check_integrity [ipx::current_core]
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INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
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INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
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INFO: [IP_Flow 19-2187] The Product Guide file is missing.
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INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
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# ipx::save_core [ipx::current_core]
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# update_ip_catalog
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# close_project
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:18:13 2019...
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
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[15:18] rainbow:minip4% cd $P4_PROJECT_DIR && make uninstall_sdnet && make install_sdnet
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***** DONE run step 8: just copies a python script
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[15:18] rainbow:minip4% cd $NF_DESIGN_DIR/test/sim_switch_default && make
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rm -f config_writes.py*
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rm -f *.pyc
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cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py ./
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[15:18] rainbow:sim_switch_default%
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***** TODO run step 9: sume simulation: fails with various errors, python and cp failures
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cd $SUME_FOLDER
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./tools/scripts/nf_test.py sim --major switch --minor default
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****** TODO python indent bug
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# update_compile_order -fileset sim_1
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update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
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al = 21975 ; free virtual = 33161
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loading libsume..
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
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fault/run.py", line 42, in <module>
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import config_writes
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
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fault/config_writes.py", line 7
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^
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IndentationError: expected an indented block
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while executing
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"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
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invoked from within
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"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_s
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ume_switch_sim.tcl" line 177)
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:21:21 2019...
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-> inserting pass in def config_tables()
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****** DONE post python cp error: different error after fixing python
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=== Work directory is /tmp/nico/test/simple_sume_switch
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=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
|
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
|
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
|
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
|
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
|
||||
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
|
||||
=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
|
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[15:21] rainbow:P4-NetFPGA%
|
||||
|
||||
**** TODO Understand which steps do what for netfpga
|
||||
**** TODO Understand a bit of xilinx/netfpga/vivado
|
||||
- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
|
||||
|
||||
|
||||
The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions
|
||||
for each option are available in Table 5-2, page 102.
|
||||
|
||||
This command parses the VHDL source file(s) and stores the parsed dump into a HDL library
|
||||
on disk.
|
||||
***** xelab
|
||||
xelab
|
||||
The xelab command, for given top-level units, does the following:
|
||||
• Loads children design units using language binding rules or the –L <library>
|
||||
command line specified HDL libraries
|
||||
• Performs a static elaboration of the design (sets parameters, generics, puts generate
|
||||
statements into effect, and so forth)
|
||||
• Generates executable code
|
||||
• Links the generated executable code with the simulation kernel library to create an
|
||||
executable simulation snapshot
|
||||
You then use the produced executable simulation snapshot name as an option to the xsim
|
||||
command along with other options to effect HDL simulation
|
||||
***** Summary of xilinx toolchain
|
||||
VHDL->[via xvhdl]-> HDL
|
||||
Verilog->[via xvlog]->HDL
|
||||
|
||||
|
||||
***** TODO Understand SimpleSumeSwitch
|
||||
SimpleSumeSwitch(
|
||||
TopParser(),
|
||||
TopPipe(),
|
||||
TopDeparser()
|
||||
) main;
|
||||
**** TODO Understand the different switch models (?)
|
||||
** NAT64/NAT46 Features in jool and tayga
|
||||
*** TODO Static 1:1 NAT46: translate from IPv4 to IPv6 with a table
|
||||
**** TODO TCP
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ fi
|
|||
|
||||
```
|
||||
|
||||
### Compile the NetPFGA drivers
|
||||
### Compile "SUME hardware library cores and some software to access registers"
|
||||
|
||||
|
||||
```
|
||||
|
|
@ -101,8 +101,24 @@ cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make
|
|||
cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
|
||||
cd $SUME_SDNET/sw/sume && make
|
||||
cd $SUME_FOLDER && make
|
||||
```
|
||||
|
||||
### Compile SUME drivers
|
||||
|
||||
```
|
||||
cd $DRIVER_FOLDER
|
||||
make all
|
||||
sudo make install
|
||||
sudo modprobe sume_riffa
|
||||
lsmod | grep sume_riffa
|
||||
```
|
||||
|
||||
### Install packages for P4
|
||||
|
||||
```
|
||||
root@loch:~# apt install python-scapy
|
||||
```
|
||||
|
||||
|
||||
## Known / encountered BUGS
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue