Rewrite the netpfga p4 program
This commit is contained in:
Nico Schottelius
parent
fb37c96a3b
commit
6e162ca63b
3 changed files with 283 additions and 3 deletions
150
doc/plan.org
150
doc/plan.org
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@ -6099,7 +6099,156 @@ nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switc
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#+END_CENTER
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*** DONE 2019-07-23: check: switch_calc compiles
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CLOSED: [2019-07-23 Tue 08:59]
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*** TODO Reset project to plain send-to-port1 code, no includes
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*** TODO 2019-07-23: merge/migrate code into switch calc until it breaks
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*** TODO 2019-07-23: install xilinx & co. to eth2.nico.ungleich.cloud -> 2nd compiler [MANUAL]
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**** DONE Install SDNET via xsetup
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CLOSED: [2019-07-23 Tue 11:03]
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**** DONE Not enough space for installing vivado (40g+ required)
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CLOSED: [2019-07-23 Tue 11:16]
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#+BEGIN_CENTER
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root@ESPRIMO-P956:~# mount /dev/sdb3 /mnt/
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root@ESPRIMO-P956:~# df -h
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Filesystem Size Used Avail Use% Mounted on
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udev 7.0G 0 7.0G 0% /dev
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tmpfs 1.4G 146M 1.3G 11% /run
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/dev/sda5 100G 62G 34G 65% /
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tmpfs 7.0G 192K 7.0G 1% /dev/shm
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tmpfs 5.0M 4.0K 5.0M 1% /run/lock
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tmpfs 7.0G 0 7.0G 0% /sys/fs/cgroup
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/dev/sda2 96M 29M 68M 30% /boot/efi
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tmpfs 1.4G 36K 1.4G 1% /run/user/108
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tmpfs 1.4G 0 1.4G 0% /run/user/1000
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tmpfs 1.4G 0 1.4G 0% /run/user/1001
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/dev/sdb3 666G 122G 510G 20% /mnt
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#+END_CENTER
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Need to move install files to different partition
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**** DONE Install Vivado via xsetup
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CLOSED: [2019-07-23 Tue 11:53]
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**** DONE Install netpfga-live repo: mkdir + git clone
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CLOSED: [2019-07-23 Tue 11:20]
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- git@github.com:NetFPGA/P4-NetFPGA-live.git to ~/project/P4-NetFPGA
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#+BEGIN_CENTER
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nico@ESPRIMO-P956:~$ mkdir ~/projects
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nico@ESPRIMO-P956:~$ cd ~/projects/
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nico@ESPRIMO-P956:~/projects$ git clone git@github.com:NetFPGA/P4-NetFPGA-live.git
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Cloning into 'P4-NetFPGA-live'...
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The authenticity of host 'github.com (140.82.118.4)' can't be established.
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RSA key fingerprint is SHA256:nThbg6kXUpJWGl7E1IGOCspRomTxdCARLviKw6E5SY8.
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Are you sure you want to continue connecting (yes/no)? yes
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Warning: Permanently added 'github.com,140.82.118.4' (RSA) to the list of known hosts.
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remote: Enumerating objects: 1822, done.
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remote: Total 1822 (delta 0), reused 0 (delta 0), pack-reused 1822
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Receiving objects: 100% (1822/1822), 6.00 MiB | 3.20 MiB/s, done.
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Resolving deltas: 100% (970/970), done.
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Checking connectivity... done.
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nico@ESPRIMO-P956:~/projects$
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#+END_CENTER
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**** DONE Change ~/projects/P4-NetFPGA/tools/settings.sh for minip4
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CLOSED: [2019-07-23 Tue 11:59]
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#+BEGIN_CENTER
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#export P4_PROJECT_NAME=switch_calc
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export P4_PROJECT_NAME=minip4
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export NF_PROJECT_NAME=simple_sume_switch
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export SUME_FOLDER=${HOME}/projects/P4-NetFPGA
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export SUME_SDNET=${SUME_FOLDER}/contrib-projects/sume-sdnet-switch
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export P4_PROJECT_DIR=${SUME_SDNET}/projects/${P4_PROJECT_NAME}
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export LD_LIBRARY_PATH=${SUME_SDNET}/sw/sume:${LD_LIBRARY_PATH}
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export PROJECTS=${SUME_FOLDER}/projects
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export DEV_PROJECTS=${SUME_FOLDER}/contrib-projects
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export IP_FOLDER=${SUME_FOLDER}/lib/hw/std/cores
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export CONTRIB_IP_FOLDER=${SUME_FOLDER}/lib/hw/contrib/cores
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export CONSTRAINTS=${SUME_FOLDER}/lib/hw/std/constraints
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export XILINX_IP_FOLDER=${SUME_FOLDER}/lib/hw/xilinx/cores
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export NF_DESIGN_DIR=${P4_PROJECT_DIR}/${NF_PROJECT_NAME}
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export NF_WORK_DIR=/tmp/${USER}
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export PYTHONPATH=.:${SUME_SDNET}/bin:${SUME_FOLDER}/tools/scripts/:${NF_DESIGN_DIR}/lib/Python:${SUME_FOLDER}/tools/scripts/NFTest
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export DRIVER_NAME=sume_riffa_v1_0_0
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export DRIVER_FOLDER=${SUME_FOLDER}/lib/sw/std/driver/${DRIVER_NAME}
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export APPS_FOLDER=${SUME_FOLDER}/lib/sw/std/apps/${DRIVER_NAME}
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export HWTESTLIB_FOLDER=${SUME_FOLDER}/lib/sw/std/hwtestlib
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#+END_CENTER
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**** DONE Allow password less sudo
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CLOSED: [2019-07-23 Tue 11:17]
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⚡ root root cat /etc/sudoers.d/nico
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nico ALL=(ALL) NOPASSWD: ALL
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**** DONE Install git
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CLOSED: [2019-07-23 Tue 11:07]
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**** Install python-scapy
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**** DONE Install master thesis repo: git clone git@gitlab.ethz.ch:nicosc/master-thesis.git
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CLOSED: [2019-07-23 Tue 11:20]
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**** DONE Setup path sourcing in ~/.bashrc
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CLOSED: [2019-07-23 Tue 12:05]
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#+BEGIN_CENTER
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nico@ESPRIMO-P956:~$ tail -n 2 .bashrc
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. ~/master-thesis/netpfga/bashinit
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#+END_CENTER
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**** DONE Setup bind mount / links / paths for compiling minip4
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CLOSED: [2019-07-23 Tue 12:05]
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nico@ESPRIMO-P956:~/projects/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects$ ln -s ~/master-thesis/netpfga/minip4/nico@ESPRIMO-P956:~/projects/P4-NetFPGA-live/contrib-projects/sume-sdnet-switch/projects$
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**** DONE Compile sume library
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CLOSED: [2019-07-23 Tue 12:07]
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#+BEGIN_CENTER
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cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make
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cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
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cd $SUME_SDNET/sw/sume && make
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cd $SUME_FOLDER && make
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#+END_CENTER
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**** TODO Install build deps
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#+BEGIN_CENTER
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sudo apt-get -y install python-matplotlib
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sudo apt-get -y install python-pip
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sudo pip install ascii_graph
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sudo apt-get install -y libc6-dev-i386
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sudo apt install -y libc6-dev
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#+END_CENTER
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*** 2019-07-23: compiling on ISG computer
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**** DONE try1: "souce" files: / missing sumereg
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CLOSED: [2019-07-23 Tue 12:14]
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#+BEGIN_CENTER
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cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
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cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
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/usr/bin/ld: cannot find -lsumereg
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collect2: error: ld returned 1 exit status
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Makefile:52: recipe for target 'libcam' failed
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make[1]: *** [libcam] Error 1
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make[1]: Leaving directory '/home/nico/master-thesis/netpfga/minip4/sw/CLI'
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ERROR: could not compile libcam souce files
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#+END_CENTER
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**** TODO try2: includes missing
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#+BEGIN_CENTER
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/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/master-thesis/netpfga/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
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In file included from /usr/include/stdio.h:27:0,
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from ./Testbench/CAM.c:30:
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/usr/include/features.h:367:25: fatal error: sys/cdefs.h: No such file or directory
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# include <sys/cdefs.h>
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^
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compilation terminated.
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ERROR: [XSIM 43-3409] Failed to compile generated C file ./Testbench/CAM.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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nico@ESPRIMO-P956:~$
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nico@nsg-System:~/master-thesis/netpfga/log$ dpkg -S /usr/include/sys/cdefs.h
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libc6-dev-i386: /usr/include/sys/cdefs.h
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#+END_CENTER
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*** the config writes madness
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- step9 (sume simulation, the longest step) in the process calls
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"config_writes.py"
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@ -6119,7 +6268,6 @@ nico@nsg-System:~/master-thesis/netpfga/minip4/simple_sume_switch/test/sim_switc
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responsible for writing the content, which in turn uses
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axi4_lite_master_write_request_control
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**** More notes for the config writes madness
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xsc and xelab are described in
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https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiGqfiAmcjjAhXEC-wKHW3_C78QFjABegQIBBAC&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2014_4%2Fug900-vivado-logic-simulation.pdf&usg=AOvVaw1jgWuqcjeph5qOplb4eJMq
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@ -7,7 +7,7 @@ echo "First source all variables and THEN run this script"
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read something
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LOG=~/master-thesis/netpfga/log/compile-$(date +%F-%H%M%S)
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exec | tee "$LOG"
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exec > "$LOG"
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exec 2>&1
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# Step 1..3: create code
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@ -1 +0,0 @@
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minip4_solution-mirror.p4
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133
p4src/minip4_solution.p4
Normal file
133
p4src/minip4_solution.p4
Normal file
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@ -0,0 +1,133 @@
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#include <core.p4>
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#include <sume_switch.p4>
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#include "headers.p4"
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/********************************************************************************
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* Header
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*/
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typedef bit<48> EthAddr_t;
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header Ethernet_h {
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EthAddr_t dstAddr;
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EthAddr_t srcAddr;
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bit<16> etherType;
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}
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struct Parsed_packet {
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Ethernet_h ethernet;
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}
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// user defined metadata: can be used to share information between
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// TopParser, TopPipe, and TopDeparser
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struct user_metadata_t {
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bit<8> unused;
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}
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// digest_data, MUST be 256 bits -- what is this used for?
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struct digest_data_t {
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bit<256> unused;
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}
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/********************************************************************************
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* Parser
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*/
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@Xilinx_MaxPacketRegion(1024)
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parser TopParser(packet_in b,
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out Parsed_packet p,
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out user_metadata_t user_metadata,
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out digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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state start {
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b.extract(p.ethernet);
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user_metadata.unused = 0;
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digest_data.unused = 0;
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transition accept;
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}
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}
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/********************************************************************************
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* Main
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*/
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control TopPipe(inout Parsed_packet p,
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inout user_metadata_t user_metadata,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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action swap_eth_addresses() {
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EthAddr_t temp = p.ethernet.dstAddr;
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p.ethernet.dstAddr = p.ethernet.srcAddr;
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p.ethernet.srcAddr = temp;
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/* set egress port */
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sume_metadata.dst_port = sume_metadata.src_port;
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}
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action send_to_port1() {
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sume_metadata.dst_port = 1;
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}
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action send_to_all_ports() {
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/* Taken from commands.txt of the "int" project:
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table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
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python convert:
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>>> 0b01010101
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85
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*/
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sume_metadata.dst_port = 85;
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}
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action do_nothing() {
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EthAddr_t temp = p.ethernet.dstAddr;
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}
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table lookup_table {
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key = {
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p.ethernet.dstAddr: exact;
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}
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actions = {
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swap_eth_addresses;
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do_nothing;
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send_to_port1;
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send_to_all_ports;
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}
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size = 64;
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// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
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default_action = send_to_port1; // test_port1()
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// default_action = send_to_all_ports; // test_allports():
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}
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apply {
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lookup_table.apply();
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}
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}
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/********************************************************************************
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* Deparser
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*/
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@Xilinx_MaxPacketRegion(1024)
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control TopDeparser(packet_out b,
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in Parsed_packet p,
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in user_metadata_t user_metadata,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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apply {
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b.emit(p.ethernet);
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}
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}
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/********************************************************************************
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* Switch
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*/
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SimpleSumeSwitch(
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TopParser(),
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TopPipe(),
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TopDeparser()
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) main;
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