compress logs
Signed-off-by: Nico Schottelius <nico@nico-notebook.schottelius.org>
This commit is contained in:
Nico Schottelius
parent
35824613af
commit
d77a88aeb4
260 changed files with 0 additions and 662993 deletions
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@ -1,100 +0,0 @@
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--- minip4_solution-mirror.p4 2019-07-23 23:17:55.151317107 +0200
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+++ minip4_solution.p4 2019-07-24 09:11:13.430196299 +0200
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@@ -4,8 +4,8 @@
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typedef bit<48> EthAddr_t;
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header Ethernet_h {
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- EthAddr_t dstAddr;
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- EthAddr_t srcAddr;
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+ EthAddr_t dst_addr;
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+ EthAddr_t src_addr;
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bit<16> etherType;
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}
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@@ -30,14 +30,14 @@
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@Xilinx_MaxPacketRegion(1024)
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parser TopParser(
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- packet_in b,
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- out Parsed_packet p,
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+ packet_in packet,
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+ out Parsed_packet hdr,
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out user_metadata_t user_metadata,
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out digest_data_t digest_data,
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- inout sume_metadata_t sume_metadata) {
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+ inout sume_metadata_t standard_metadata) {
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state start {
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- b.extract(p.ethernet);
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+ packet.extract(hdr.ethernet);
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user_metadata.unused = 0;
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digest_data.unused = 0;
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@@ -45,19 +45,20 @@
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}
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}
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+
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/********************************************************************************
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* Main
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*/
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control TopPipe(
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- inout Parsed_packet p,
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+ inout Parsed_packet hdr,
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inout user_metadata_t user_metadata,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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action swap_eth_addresses() {
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- EthAddr_t temp = p.ethernet.dstAddr;
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- p.ethernet.dstAddr = p.ethernet.srcAddr;
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- p.ethernet.srcAddr = temp;
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+ EthAddr_t temp = hdr.ethernet.dst_addr;
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+ hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
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+ hdr.ethernet.src_addr = temp;
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/* set egress port */
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sume_metadata.dst_port = sume_metadata.src_port;
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@@ -80,12 +81,12 @@
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}
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action do_nothing() {
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- EthAddr_t temp = p.ethernet.dstAddr;
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+ EthAddr_t temp = hdr.ethernet.dst_addr;
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}
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table lookup_table {
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key = {
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- p.ethernet.dstAddr: exact;
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+ hdr.ethernet.dst_addr: exact;
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}
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actions = {
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@@ -109,15 +110,17 @@
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@Xilinx_MaxPacketRegion(1024)
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control TopDeparser(
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- packet_out b,
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- in Parsed_packet p,
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+ packet_out packet,
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+ in Parsed_packet hdr,
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in user_metadata_t user_metadata,
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inout digest_data_t digest_data,
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inout sume_metadata_t sume_metadata) {
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apply {
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- b.emit(p.ethernet);
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+ packet.emit(hdr.ethernet);
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}
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+
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+
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}
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/********************************************************************************
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@@ -128,4 +131,4 @@
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TopParser(),
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TopPipe(),
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TopDeparser()
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-) main;
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+) main;
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\ No newline at end of file
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+ date
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Die Jul 23 12:29:36 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(59):syntax error, unexpected IDENTIFIER, expecting STATE
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digest_data
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^^^^^^^^^^^
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error: 1 errors encountered, aborting compilation
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 12:30:28 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(59):syntax error, unexpected IDENTIFIER, expecting STATE
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digest_data
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^^^^^^^^^^^
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error: 1 errors encountered, aborting compilation
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 12:33:35 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(78)
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EthAddr_t temp = hdr.ethernet.dstAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(79)
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hdr.ethernet.dstAddr = hdr.ethernet.srcAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field srcAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(79)
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hdr.ethernet.dstAddr = hdr.ethernet.srcAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field srcAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(80)
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hdr.ethernet.srcAddr = temp;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(103)
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EthAddr_t temp = hdr.ethernet.dstAddr;
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^^^^^^^
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headers.p4(86): error: Structure header ethernet_t does not have a field dstAddr
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header ethernet_t {
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^^^^^^^^^^
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minip4_solution.p4(108)
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hdr.ethernet.dstAddr: exact;
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^^^^^^^
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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Makefile:31: recipe for target 'frontend' failed
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 16:08:15 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_23255.backup.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_23255.backup.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log
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rm -f sw/config_tables.c
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make -C src/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
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minip4_solution.p4(274): error: main: Cannot unify struct user_metadata_t to struct metadata
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) main;
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^^^^
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Makefile:34: recipe for target 'all' failed
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make[1]: *** [all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make: *** [frontend] Error 2
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+ date
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Die Jul 23 16:10:50 CEST 2019
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+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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+ make
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make -C src/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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rm -f *.sdnet *.tbl .sdnet_switch_info.dat
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
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make -C testdata/ clean
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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rm -rf nf_sume_sdnet_ip/
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rm -f
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rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
./gen_testdata.py
|
|
||||||
Applying pkt on nf0 at 1:
|
|
||||||
Applying pkt on nf1 at 2:
|
|
||||||
Applying pkt on nf2 at 3:
|
|
||||||
Applying pkt on nf3 at 4:
|
|
||||||
nf0_applied times: [1]
|
|
||||||
nf1_applied times: [2]
|
|
||||||
nf2_applied times: [3]
|
|
||||||
nf3_applied times: [4]
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
|
|
||||||
Xilinx SDNet Compiler version 2018.2, build 2342300
|
|
||||||
|
|
||||||
Compilation successful
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
|
|
||||||
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
|
|
||||||
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
|
|
||||||
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
|
|
||||||
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
|
|
||||||
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
|
|
||||||
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
|
|
||||||
# Fix introduced for SDNet 2017.4
|
|
||||||
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
|
|
||||||
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
# Fix introduced for SDNet 2018.2
|
|
||||||
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
+ date
|
|
||||||
Die Jul 23 16:10:53 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
|
|
||||||
+ ./vivado_sim.bash
|
|
||||||
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
|
|
||||||
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_0_t.HDL/TopPipe_lvl_0_t.vp" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_Engine
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_0
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_lookup_table_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_1
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_do_nothing_0_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_sume_metadata_dst_port
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_all_ports_0_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_sume_metadata_dst_port
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_send_to_port1_0_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_TopPipe_fl_temp
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_dst_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_hdr_ethernet_src_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_sume_metadata_dst_port
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_swap_eth_addresses_0_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_EngineStage_2
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_0_t_sink_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for__OUT_.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_SYNCER_for__OUT_
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_S_SYNCER_for_TopDeparser.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_S_SYNCER_for_TopDeparser
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_fifo.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|
||||||
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module glbl
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopDeparser.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopDeparser
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/S_SYNCER_for_TopParser.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_SYNCER_for_TopParser
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp" into library work
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_base
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_rst
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_counter_updn
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_vec
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_reg_bit
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_reg_pipe_bit
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_sync
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_async
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_fifo_axis
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|
||||||
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module glbl
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_BRIDGER_for_lookup_table_tuple_in_request
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.vp" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_Engine
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_EngineStage_0
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_lookup_table_req_lookup_request_key
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t_setup_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopPipe_lvl_t.HDL/TopPipe_lvl_t.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopPipe_lvl_t
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_base
|
|
||||||
INFO: [VRFC 10-311] analyzing module asym_bwe_bb
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dpdistram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_dprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sdpram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_spram
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_sprom
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_memory_tdpram
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_cdc.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_gray
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_handshake
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_pulse
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_array_single
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_sync_rst
|
|
||||||
INFO: [VRFC 10-311] analyzing module xpm_cdc_async_rst
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.vp" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Wrap
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_IntTop
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Lookup
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Lookup
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_RamR1RW1
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Cam
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Update
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Hash_Update
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod4_Rnd
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_Randmod5_Rnd
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t_csr
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/lookup_table_t.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module lookup_table_t
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp" into library work
|
|
||||||
ERROR: [VRFC 10-1491] unexpected EOF [/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp:37]
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_CONTROLLER_SimpleSumeSwitch
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TB_System_Stim
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module Check
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch_tb
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.vp" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_Engine
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_ErrorCheck
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_remove
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_extract_headers_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoWriter
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DscFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_LatencyBuffer
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_PktFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_FifoReader
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterUp
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataShift_UniShifterSelect
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_BarrelShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataBuffer_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_UniShifterUp
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_0_Editor_DataMux
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_1_ErrorCheck
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_act_sec_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_ErrorCheck
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_insert
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_dst_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_src_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute__STRUCT_ethertype
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_emit_0_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoWriter
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DscFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_LatencyBuffer
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_PktFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleFifo_RAM
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_FifoReader
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterUp
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataShift_UniShifterSelect
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_BarrelShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataBuffer_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownMask
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleMerge_UniShifterDownTuple
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterDown
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_UniShifterUp
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_TupleShift_BidirShifterUpdate_UniShifter2X
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t_EngineStage_2_Editor_DataMux
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopDeparser_t.HDL/TopDeparser_t.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopDeparser_t
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_line.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_RESETTER_line
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_lookup.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_RESETTER_lookup
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_RESETTER.HDL/S_RESETTER_control.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_RESETTER_control
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.vp" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_Engine
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ErrorCheck
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_ExtractShifter
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_isValid
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_dst_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_src_addr
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_hdr_ethernet_ethertype
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_TopParser_extracts_size
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_user_metadata_unused
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_digest_data_unused
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_start_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_reject
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_reject_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_0_TupleForward
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_EngineStage_1_ErrorCheck
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_accept
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_nextSection
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t_accept_compute_control_increment_offset
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/TopParser_t.HDL/TopParser_t.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module TopParser_t
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_EGRESS
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp" into library work
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp" into library work
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module S_PROTOCOL_ADAPTER_INGRESS
|
|
||||||
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.v" into library work
|
|
||||||
INFO: [VRFC 10-311] analyzing module SimpleSumeSwitch
|
|
||||||
+ true
|
|
||||||
+ mkdir -p xsim.dir/xsc
|
|
||||||
+ find -name '*.c'
|
|
||||||
+ xargs /opt/Xilinx/Vivado/2018.2/bin/xsc -mt off -v 1
|
|
||||||
Turned off multi-threading.
|
|
||||||
Running compilation flow
|
|
||||||
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/CAM.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" -DXILINX_SIMULATOR
|
|
||||||
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/gcc -fPIC -c -Wa,-W -fPIC -m64 -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/ -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" -I"/opt/Xilinx/Vivado/2018.2/data/xsim/systemc" "./Testbench/user.c" -O1 -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -DXILINX_SIMULATOR
|
|
||||||
./Testbench/user.c: In function ‘register_write_control’:
|
|
||||||
./Testbench/user.c:37:5: warning: implicit declaration of function ‘SV_write_control’ [-Wimplicit-function-declaration]
|
|
||||||
SV_write_control(&sv_addr, &sv_data);
|
|
||||||
^~~~~~~~~~~~~~~~
|
|
||||||
./Testbench/user.c: In function ‘register_read_control’:
|
|
||||||
./Testbench/user.c:51:5: warning: implicit declaration of function ‘SV_read_control’ [-Wimplicit-function-declaration]
|
|
||||||
SV_read_control(&sv_addr, &sv_data);
|
|
||||||
^~~~~~~~~~~~~~~
|
|
||||||
./Testbench/user.c: In function ‘CAM_Init’:
|
|
||||||
./Testbench/user.c:88:76: warning: passing argument 9 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|
||||||
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|
||||||
^~~~~~~~~~~~~~
|
|
||||||
In file included from ./Testbench/user.c:7:0:
|
|
||||||
./Testbench/CAM.h:169:5: note: expected ‘void (*)(addr_t, uint32_t) {aka void (*)(long long unsigned int, unsigned int)}’ but argument is of type ‘void (*)(uint32_t, uint32_t) {aka void (*)(unsigned int, unsigned int)}’
|
|
||||||
int CAM_Init_ValidateContext(
|
|
||||||
^~~~~~~~~~~~~~~~~~~~~~~~
|
|
||||||
./Testbench/user.c:88:92: warning: passing argument 10 of ‘CAM_Init_ValidateContext’ from incompatible pointer type [-Wincompatible-pointer-types]
|
|
||||||
if(CAM_Init_ValidateContext(cx,baseAddr,256,depth,k,clk_period,v,aging,register_write, register_read, &log_msg, log_level))
|
|
||||||
^~~~~~~~~~~~~
|
|
||||||
In file included from ./Testbench/user.c:7:0:
|
|
||||||
./Testbench/CAM.h:169:5: note: expected ‘uint32_t (*)(addr_t) {aka unsigned int (*)(long long unsigned int)}’ but argument is of type ‘uint32_t (*)(uint32_t) {aka unsigned int (*)(unsigned int)}’
|
|
||||||
int CAM_Init_ValidateContext(
|
|
||||||
^~~~~~~~~~~~~~~~~~~~~~~~
|
|
||||||
Done compilation
|
|
||||||
Linking with command:
|
|
||||||
/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|
||||||
|
|
||||||
Running command : /opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/g++ -Wa,-W -O -fPIC -m64 -shared -o "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/CAM.lnx64.o" "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work/xsc/user.lnx64.o" -L/opt/Xilinx/Vivado/2018.2/lib/lnx64.o -lrdi_simulator_kernel -lrdi_xsim_systemc -B/opt/Xilinx/Vivado/2018.2/lib/lnx64.o/../../tps/lnx64/gcc-6.2.0/bin/../../binutils-2.26/bin/
|
|
||||||
Done linking: "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/dpi.so"
|
|
||||||
+ /opt/Xilinx/Vivado/2018.2/bin/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|
||||||
Vivado Simulator 2018.2
|
|
||||||
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
|
||||||
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -L work --debug all -sv_lib dpi.so SimpleSumeSwitch_tb glbl
|
|
||||||
Multi-threading is on. Using 6 slave threads.
|
|
||||||
Starting static elaboration
|
|
||||||
Completed static elaboration
|
|
||||||
Starting simulation data flow analysis
|
|
||||||
Completed simulation data flow analysis
|
|
||||||
Time Resolution for simulation is 1ps
|
|
||||||
Compiling module work.S_RESETTER_line
|
|
||||||
Compiling module work.S_RESETTER_lookup
|
|
||||||
Compiling module work.S_RESETTER_control
|
|
||||||
Compiling module work.TopParser_t_EngineStage_0_ErrorC...
|
|
||||||
Compiling module work.TopParser_t_EngineStage_0_Extrac...
|
|
||||||
Compiling module work.TopParser_t_start_compute_hdr_et...
|
|
||||||
Compiling module work.TopParser_t_start_compute_hdr_et...
|
|
||||||
Compiling module work.TopParser_t_start_compute_hdr_et...
|
|
||||||
Compiling module work.TopParser_t_start_compute_hdr_et...
|
|
||||||
Compiling module work.TopParser_t_start_compute_TopPar...
|
|
||||||
Compiling module work.TopParser_t_start_compute_user_m...
|
|
||||||
Compiling module work.TopParser_t_start_compute_digest...
|
|
||||||
Compiling module work.TopParser_t_start_compute_contro...
|
|
||||||
Compiling module work.TopParser_t_start_compute_contro...
|
|
||||||
Compiling module work.TopParser_t_start
|
|
||||||
Compiling module work.TopParser_t_reject_compute_contr...
|
|
||||||
Compiling module work.TopParser_t_reject_compute_contr...
|
|
||||||
Compiling module work.TopParser_t_reject
|
|
||||||
Compiling module work.TopParser_t_EngineStage_0_TupleF...
|
|
||||||
Compiling module work.TopParser_t_EngineStage_0
|
|
||||||
Compiling module work.TopParser_t_EngineStage_1_ErrorC...
|
|
||||||
Compiling module work.TopParser_t_accept_compute_contr...
|
|
||||||
Compiling module work.TopParser_t_accept_compute_contr...
|
|
||||||
Compiling module work.TopParser_t_accept
|
|
||||||
Compiling module work.TopParser_t_EngineStage_1
|
|
||||||
Compiling module work.TopParser_t_Engine
|
|
||||||
Compiling module work.TopParser_t
|
|
||||||
Compiling module work.TopPipe_lvl_t_setup_compute_look...
|
|
||||||
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
|
|
||||||
Compiling module work.TopPipe_lvl_t_setup_compute_cont...
|
|
||||||
Compiling module work.TopPipe_lvl_t_setup
|
|
||||||
Compiling module work.TopPipe_lvl_t_EngineStage_0
|
|
||||||
Compiling module work.TopPipe_lvl_t_Engine
|
|
||||||
Compiling module work.TopPipe_lvl_t
|
|
||||||
Compiling module work.lookup_table_t_Hash_Lookup
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_SIZE=880,...
|
|
||||||
Compiling module work.xpm_memory_tdpram(MEMORY_SIZE=88...
|
|
||||||
Compiling module work.lookup_table_t_RamR1RW1
|
|
||||||
Compiling module work.lookup_table_t_Cam
|
|
||||||
Compiling module work.lookup_table_t_Lookup
|
|
||||||
Compiling module work.lookup_table_t_Hash_Update
|
|
||||||
Compiling module work.lookup_table_t_Randmod4_Rnd
|
|
||||||
Compiling module work.lookup_table_t_Randmod4
|
|
||||||
Compiling module work.lookup_table_t_Randmod5_Rnd
|
|
||||||
Compiling module work.lookup_table_t_Randmod5
|
|
||||||
Compiling module work.lookup_table_t_Update
|
|
||||||
Compiling module work.lookup_table_t_IntTop
|
|
||||||
Compiling module work.lookup_table_t_Wrap
|
|
||||||
Compiling module work.lookup_table_t_csr
|
|
||||||
Compiling module work.lookup_table_t
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_lookup_table_sec
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_EngineStage_0
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_do_nothing_0_sec
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_all_port...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_send_to_port1_0_...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_swap_eth_address...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_EngineStage_1
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_sink_compute_con...
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_sink
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_EngineStage_2
|
|
||||||
Compiling module work.TopPipe_lvl_0_t_Engine
|
|
||||||
Compiling module work.TopPipe_lvl_0_t
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Erro...
|
|
||||||
Compiling module work.TopDeparser_t_extract_headers_se...
|
|
||||||
Compiling module work.TopDeparser_t_extract_headers_se...
|
|
||||||
Compiling module work.TopDeparser_t_extract_headers_se...
|
|
||||||
Compiling module work.TopDeparser_t_extract_headers_se...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_0
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_1_Erro...
|
|
||||||
Compiling module work.TopDeparser_t_act_sec_compute_co...
|
|
||||||
Compiling module work.TopDeparser_t_act_sec_compute_co...
|
|
||||||
Compiling module work.TopDeparser_t_act_sec
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_1
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Erro...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute__ST...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0_compute_con...
|
|
||||||
Compiling module work.TopDeparser_t_emit_0
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2_Edit...
|
|
||||||
Compiling module work.TopDeparser_t_EngineStage_2
|
|
||||||
Compiling module work.TopDeparser_t_Engine
|
|
||||||
Compiling module work.TopDeparser_t
|
|
||||||
Compiling module work.xpm_cdc_sync_rst(DEST_SYNC_FF=2,...
|
|
||||||
Compiling module work.xpm_fifo_rst(COMMON_CLOCK=0)
|
|
||||||
Compiling module work.xpm_fifo_reg_bit
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|
||||||
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=8)
|
|
||||||
Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
|
|
||||||
Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=9)
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.S_BRIDGER_for_lookup_table_tuple...
|
|
||||||
Compiling module work.S_PROTOCOL_ADAPTER_INGRESS
|
|
||||||
Compiling module work.S_PROTOCOL_ADAPTER_EGRESS
|
|
||||||
Compiling module work.xpm_fifo_rst_default
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=1...
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=9...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_counter_updn(COUNTER_WIDTH=2...
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.S_SYNCER_for_TopParser
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.S_SYNCER_for_S_SYNCER_for_S_SYNC...
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=1...
|
|
||||||
Compiling module work.xpm_fifo_sync(FIFO_MEMORY_TYPE="...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
|
|
||||||
Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
|
|
||||||
Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_async(FIFO_MEMORY_TYPE=...
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Compiling module work.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module work.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module work.xpm_cdc_gray(DEST_SYNC_FF=2,INIT...
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Compiling module work.xpm_fifo_reg_vec(REG_WIDTH=7)
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(COMMON_CLOCK=0,FIF...
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Compiling module work.xpm_fifo_base(FIFO_MEMORY_TYPE=2...
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Compiling module work.SimpleSumeSwitch_tb
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Compiling module work.glbl
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Built simulation snapshot work.SimpleSumeSwitch_tb#work.glbl
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****** Webtalk v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-186] '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Tue Jul 23 16:11:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
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||||||
INFO: [Common 17-206] Exiting Webtalk at Tue Jul 23 16:11:37 2019...
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+ /opt/Xilinx/Vivado/2018.2/bin/xsim --runall SimpleSumeSwitch_tb#work.glbl
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****** xsim v2018.2 (64-bit)
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||||||
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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||||||
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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||||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
||||||
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|
||||||
source xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsim_script.tcl
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||||||
# xsim {work.SimpleSumeSwitch_tb#work.glbl} -autoloadwcfg -runall
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|
||||||
Vivado Simulator 2018.2
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||||||
Time resolution is 1 ps
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||||||
run -all
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||||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_0.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_0/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_232 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_1.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_1/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_232 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_2.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_2/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_232 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_3.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_3/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_232 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.lookup_table.lookup_table_t_Wrap_inst.lookup_table_t_IntTop_inst.lookup_table_t_Lookup_inst.lookup_table_t_RamR1RW1_KeyValue_inst_4.xpm_memory_tdpram_inst.xpm_memory_base_inst.config_drc
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/lookup_table/lookup_table_t_Wrap_inst/lookup_table_t_IntTop_inst/lookup_table_t_Lookup_inst/lookup_table_t_RamR1RW1_KeyValue_inst_4/xpm_memory_tdpram_inst/xpm_memory_base_inst/Initial270_232 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_BRIDGER_for_lookup_table_tuple_in_request.myfifo.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_BRIDGER_for_lookup_table_tuple_in_request/myfifo/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_937 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.y2085gicmudugvlktsbnh_2174.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/y2085gicmudugvlktsbnh_2174/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.n6blk9hlqp687lg4pjoglgl5i5p_2339.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/n6blk9hlqp687lg4pjoglgl5i5p_2339/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1060 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.o3aymqua8jkrq54gqv239eqzvm42_2136.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/o3aymqua8jkrq54gqv239eqzvm42_2136/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1124 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopParser.t9kzthoevx639owk0fs_2043.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopParser/t9kzthoevx639owk0fs_2043/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1208 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.hvatbl4angxq7on5tul_1753.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/hvatbl4angxq7on5tul_1753/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.mktmuiiuyajbgn91_1912.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/mktmuiiuyajbgn91_1912/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1060 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.hh047zzwshbvbjjivbkho_1995.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/hh047zzwshbvbjjivbkho_1995/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1389 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.edizh3q16l8igp52s15q1brjme2v_1572.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/edizh3q16l8igp52s15q1brjme2v_1572/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1473 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.z2sja1mpyuvwzszsw_117.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/z2sja1mpyuvwzszsw_117/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1557 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.dv1hd492ukhesjn3oe7u29k_728.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/dv1hd492ukhesjn3oe7u29k_728/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1124 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.zpkn8gdfgaynosnt9va3zsq3vx6ht_2192.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/zpkn8gdfgaynosnt9va3zsq3vx6ht_2192/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1208 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser.d56p4qwkkyy94c5885h3lgrk46q0czcd_25.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_S_SYNCER_for_TopDeparser/d56p4qwkkyy94c5885h3lgrk46q0czcd_25/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1809 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.nas4rg3pux7o1aro7kzl1yd37q7p3d_1547.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/nas4rg3pux7o1aro7kzl1yd37q7p3d_1547/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ldf62cj3z8stmk06qwica77kfmkt_1524.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ldf62cj3z8stmk06qwica77kfmkt_1524/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1060 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.yfjtnonynsefr9zqcjur0fzffy4_525.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/yfjtnonynsefr9zqcjur0fzffy4_525/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1996 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.skwrd65y3wdcrxpc61lbjtd_430.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/skwrd65y3wdcrxpc61lbjtd_430/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1557 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.d3qzheuvgw1mueo4q2h2gqc2oee_275.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/d3qzheuvgw1mueo4q2h2gqc2oee_275/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1389 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.vh8dlcuhnqqqd8mjknjsf2y76jyh_415.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/vh8dlcuhnqqqd8mjknjsf2y76jyh_415/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2248 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.ogjntfjgeqhdcxr8h234km80m3zq9g_661.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/ogjntfjgeqhdcxr8h234km80m3zq9g_661/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1124 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.gkmvy3foqjphd7uieg9uly0u130p88b_379.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/gkmvy3foqjphd7uieg9uly0u130p88b_379/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1473 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.u12odfalhq81jcn456eto7_662.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/u12odfalhq81jcn456eto7_662/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_2500 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.lch5dg9a6cuy8g7u77soyoiy0ljayr_2023.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/lch5dg9a6cuy8g7u77soyoiy0ljayr_2023/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1208 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_S_SYNCER_for_TopDeparser.k3prowvoaw6gewpwe5nxc9jg677_174.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_S_SYNCER_for_TopDeparser/k3prowvoaw6gewpwe5nxc9jg677_174/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1809 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.drdr0ovmq9g86vv4rg0iwyi97_1892.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/drdr0ovmq9g86vv4rg0iwyi97_1892/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1030 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.qqzubgnrk08unyvtpma_1368.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/qqzubgnrk08unyvtpma_1368/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1060 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.lllojmsye6i5hj6kyy865f1aru3b0_726.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/lllojmsye6i5hj6kyy865f1aru3b0_726/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1389 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.nadko0whz51p5ffy_2240.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/nadko0whz51p5ffy_2240/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1473 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.xysiyx4v08rj7k4lowig_648.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/xysiyx4v08rj7k4lowig_648/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1557 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.v4x75ow1659umsenzy2h5yj6hadgydl_2277.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/v4x75ow1659umsenzy2h5yj6hadgydl_2277/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1124 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.cn05exgr1oh1ch3xlo54j67_2408.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/cn05exgr1oh1ch3xlo54j67_2408/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1208 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for_TopDeparser.yg4wxxkhd68gmla2_75.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for_TopDeparser/yg4wxxkhd68gmla2_75/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1809 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.u4wfbrh67d2hn7ze_1826.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/u4wfbrh67d2hn7ze_1826/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_3354 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.ighf3mgc0h4epbw1nn_1851.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/ighf3mgc0h4epbw1nn_1851/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1060 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.qi079hn8yvzz0h1tfe17e9_584.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/qi079hn8yvzz0h1tfe17e9_584/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1557 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. SimpleSumeSwitch_tb.SimpleSumeSwitch_i.S_SYNCER_for__OUT_.kkixfnxie6l9lc6yu_826.gnuram_async_fifo.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc 0
|
|
||||||
Time: 1 ps Iteration: 0 Process: /SimpleSumeSwitch_tb/SimpleSumeSwitch_i/S_SYNCER_for__OUT_/kkixfnxie6l9lc6yu_826/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/Initial270_1124 File: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/lookup_table_t.HDL/xpm_memory.sv
|
|
||||||
[SW] CAM_Init() - start
|
|
||||||
[SW] CAM_Init() - done
|
|
||||||
SV_write_control()- start
|
|
||||||
[SW] CAM_EnableDevice() - start
|
|
||||||
SV_write_control()- done
|
|
||||||
SV_read_control()- start
|
|
||||||
SV_read_control()- done
|
|
||||||
SV_write_control()- start
|
|
||||||
SV_write_control()- done
|
|
||||||
[SW] CAM_EnableDevice() - done
|
|
||||||
[2280754] INFO: finished packet stimulus file
|
|
||||||
[2735572] INFO: packet 1 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
|
|
||||||
[2735572] INFO: packet 1 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
|
|
||||||
[2738904] INFO: packet 1 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
|
|
||||||
[2745568] INFO: packet 2 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001040000 >
|
|
||||||
[2745568] INFO: packet 2 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
|
|
||||||
[2748900] INFO: packet 2 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
|
|
||||||
[2755564] INFO: packet 3 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001100000 >
|
|
||||||
[2755564] INFO: packet 3 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
|
|
||||||
[2758896] INFO: packet 3 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
|
|
||||||
[2765560] INFO: packet 4 tuple OK < tuple_out_digest_data, tuple_out_standard_metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001400000 >
|
|
||||||
[2765560] INFO: packet 4 data OK (tlast, tkeep, tdata) = (0, ffffffff, 0000000000000000000000000000000000000000081111111108082222222208)
|
|
||||||
[2768892] INFO: packet 4 data OK (tlast, tkeep, tdata) = (1, ffffffff, 0000000000000000000000000000000000000000000000000000000000000000)
|
|
||||||
[6104224] INFO: stopping simulation after 1000 idle cycles
|
|
||||||
[6104224] INFO: all expected data successfully received
|
|
||||||
[6104224] INFO: TEST PASSED
|
|
||||||
$finish called at time : 6104224 ps : File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv" Line 207
|
|
||||||
exit
|
|
||||||
INFO: [Common 17-206] Exiting xsim at Tue Jul 23 16:11:47 2019...
|
|
||||||
+ grep ^expected /home/nico/master-thesis/netpfga/log/compile-2019-07-23-161050
|
|
||||||
+ sed -e s/.*= <// -e s/.*= (//
|
|
||||||
+ expected_line=
|
|
||||||
+ grep ^actual /home/nico/master-thesis/netpfga/log/compile-2019-07-23-161050
|
|
||||||
+ sed -e s/.*= <// -e s/.*= (//
|
|
||||||
+ actual_line=
|
|
||||||
+ [ != ]
|
|
||||||
+ date
|
|
||||||
Die Jul 23 16:11:47 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make config_writes
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
|
||||||
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
|
|
||||||
new dic: OrderedDict()
|
|
||||||
+ date
|
|
||||||
Die Jul 23 16:11:47 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make uninstall_sdnet
|
|
||||||
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|
||||||
+ make install_sdnet
|
|
||||||
rm -rf /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip
|
|
||||||
cp -r nf_sume_sdnet_ip /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/
|
|
||||||
mkdir /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper
|
|
||||||
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/hdl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/wrapper/
|
|
||||||
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/tcl/* /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|
||||||
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/sss_wrapper/Makefile /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|
||||||
make -C /home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|
||||||
rm -rf ip_* vivado*.* *.xml xgui/ .Xil* *.*~ *.zip
|
|
||||||
vivado -mode batch -source nf_sume_sdnet.tcl
|
|
||||||
|
|
||||||
****** Vivado v2018.2 (64-bit)
|
|
||||||
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
|
|
||||||
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
|
||||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
|
||||||
|
|
||||||
source nf_sume_sdnet.tcl
|
|
||||||
# set design nf_sume_sdnet
|
|
||||||
# set top nf_sume_sdnet
|
|
||||||
# set device xc7vx690t-3-ffg1761
|
|
||||||
# set proj_dir ./ip_proj
|
|
||||||
# set ip_version 1.00
|
|
||||||
# set lib_name NetFPGA
|
|
||||||
# create_project -name ${design} -force -dir "./${proj_dir}" -part ${device}
|
|
||||||
# set_property source_mgmt_mode All [current_project]
|
|
||||||
# set_property top ${top} [current_fileset]
|
|
||||||
# set_property ip_repo_paths $::env(SUME_FOLDER)/lib/hw/ [current_fileset]
|
|
||||||
# update_ip_catalog
|
|
||||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
||||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|
||||||
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|
||||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
|
|
||||||
# puts "nf_sume_sdnet"
|
|
||||||
nf_sume_sdnet
|
|
||||||
# read_verilog "./wrapper/sume_to_sdnet.v"
|
|
||||||
# read_verilog "./wrapper/nf_sume_sdnet.v"
|
|
||||||
# read_verilog "./wrapper/changeEndian.v"
|
|
||||||
# add_files -scan_for_includes ./SimpleSumeSwitch/
|
|
||||||
# import_files -force
|
|
||||||
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
|
|
||||||
# update_compile_order -fileset sources_1
|
|
||||||
# update_compile_order -fileset sim_1
|
|
||||||
# ipx::package_project
|
|
||||||
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/wrapper/changeEndian.v'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/SimpleSumeSwitch.h'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_INGRESS.vp'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_PROTOCOL_ADAPTERs.HDL/S_PROTOCOL_ADAPTER_EGRESS.vp'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/dpi.h'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/Check.v'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM.h'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/CAM_INST0.h'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/TB_System_Stim.v'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_CONTROLLERs.HDL/S_CONTROLLER_SimpleSumeSwitch.vp'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/glbl.v'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_cdc.sv'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_memory.sv'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/xpm_fifo.sv'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_BRIDGERs.HDL/S_BRIDGER_for_lookup_table_tuple_in_request.vp'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/glbl.v'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_cdc.sv'.
|
|
||||||
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj/nf_sume_sdnet.srcs/sources_1/imports/nf_sume_sdnet_ip/SimpleSumeSwitch/S_SYNCERs.HDL/xpm_memory.sv'.
|
|
||||||
INFO: [IP_Flow 19-5169] Module 'nf_sume_sdnet' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_resetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-5107] Inferred bus interface 'axis_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'axis_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'S_AXI'.
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'.
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'S_AXI_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'S_AXI_ARESETN'.
|
|
||||||
INFO: [IP_Flow 19-4728] Bus Interface 'axis_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'axis_resetn'.
|
|
||||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|
||||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|
||||||
# set_property name ${design} [ipx::current_core]
|
|
||||||
# set_property library ${lib_name} [ipx::current_core]
|
|
||||||
# set_property vendor_display_name {NetFPGA} [ipx::current_core]
|
|
||||||
# set_property company_url {http://www.netfpga.org} [ipx::current_core]
|
|
||||||
# set_property vendor {NetFPGA} [ipx::current_core]
|
|
||||||
# set_property supported_families {{virtex7} {Production}} [ipx::current_core]
|
|
||||||
# set_property taxonomy {{/NetFPGA/Generic}} [ipx::current_core]
|
|
||||||
# set_property version ${ip_version} [ipx::current_core]
|
|
||||||
# set_property display_name ${design} [ipx::current_core]
|
|
||||||
# set_property description ${design} [ipx::current_core]
|
|
||||||
# ipx::add_user_parameter {C_M_AXIS_DATA_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_M_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {256} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {C_S_AXIS_DATA_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_S_AXIS_DATA_WIDTH} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {256} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_DATA_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {C_M_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_M_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {128} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_M_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {C_S_AXIS_TUSER_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_S_AXIS_TUSER_WIDTH} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {128} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_S_AXIS_TUSER_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {C_S_AXI_DATA_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_S_AXI_DATA_WIDTH} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {32} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_DATA_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {C_S_AXI_ADDR_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {C_S_AXI_ADDR_WIDTH} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {12} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter C_S_AXI_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_user_parameter {SDNET_ADDR_WIDTH} [ipx::current_core]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_resolve_type {user} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property display_name {SDNET_ADDR_WIDTH} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value {11} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
WARNING: command 'get_user_parameter' will be removed in the 2015.3 release, use 'get_user_parameters' instead
|
|
||||||
# set_property value_format {long} [ipx::get_user_parameter SDNET_ADDR_WIDTH [ipx::current_core]]
|
|
||||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagesynthesis -of_objects [ipx::current_core]]
|
|
||||||
# ipx::add_subcore xilinx.com:ip:axis_data_fifo:1.1 [ipx::get_file_groups xilinx_anylanguagebehavioralsimulation -of_objects [ipx::current_core]]
|
|
||||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects [ipx::current_core]]
|
|
||||||
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects [ipx::current_core]]
|
|
||||||
# update_ip_catalog -rebuild
|
|
||||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
||||||
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/lib/hw'.
|
|
||||||
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository '/home/nico/projects/P4-NetFPGA/lib/hw' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/ip_proj'.)
|
|
||||||
# ipx::infer_user_parameters [ipx::current_core]
|
|
||||||
# ipx::check_integrity [ipx::current_core]
|
|
||||||
INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nf_sume_sdnet_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
|
|
||||||
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|
||||||
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|
||||||
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
|
|
||||||
# ipx::save_core [ipx::current_core]
|
|
||||||
# update_ip_catalog
|
|
||||||
# close_project
|
|
||||||
INFO: [Common 17-206] Exiting Vivado at Tue Jul 23 16:12:05 2019...
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip'
|
|
||||||
+ date
|
|
||||||
Die Jul 23 16:12:05 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default
|
|
||||||
+ make
|
|
||||||
make: *** No targets specified and no makefile found. Stop.
|
|
||||||
BIN
netpfga/log/compile-2019-07-23-161050.xz
Normal file
BIN
netpfga/log/compile-2019-07-23-161050.xz
Normal file
Binary file not shown.
|
|
@ -1,10 +0,0 @@
|
||||||
+ date
|
|
||||||
Die Jul 23 16:19:04 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make[1]: *** No rule to make target 'clean'. Stop.
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:71: recipe for target 'clean' failed
|
|
||||||
make: *** [clean] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-23-161904.xz
Normal file
BIN
netpfga/log/compile-2019-07-23-161904.xz
Normal file
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Load diff
BIN
netpfga/log/compile-2019-07-23-162231.xz
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BIN
netpfga/log/compile-2019-07-23-162231.xz
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BIN
netpfga/log/compile-2019-07-23-162909-metadata-meta.xz
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netpfga/log/compile-2019-07-23-162909-metadata-meta.xz
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BIN
netpfga/log/compile-2019-07-23-203337.xz
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netpfga/log/compile-2019-07-23-203337.xz
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BIN
netpfga/log/compile-2019-07-23-215654-only-port1.xz
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netpfga/log/compile-2019-07-23-215654-only-port1.xz
Normal file
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File diff suppressed because one or more lines are too long
BIN
netpfga/log/compile-2019-07-23-232231-only-renamediff-5.4.xz
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BIN
netpfga/log/compile-2019-07-23-232231-only-renamediff-5.4.xz
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File diff suppressed because one or more lines are too long
BIN
netpfga/log/compile-2019-07-24-091326-only-renamediff-5.5.xz
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BIN
netpfga/log/compile-2019-07-24-091326-only-renamediff-5.5.xz
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BIN
netpfga/log/compile-2019-07-24-095024-subparser-5.6.xz
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netpfga/log/compile-2019-07-24-095024-subparser-5.6.xz
Normal file
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|
|
@ -1,29 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 09:51:08 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(37): warning: start: implicit transition to `reject'
|
|
||||||
state start {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(39): error: Could not find declaration for user_metadata
|
|
||||||
user_metadata.unused = 0;
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-095108-subparser-5.6.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-095108-subparser-5.6.xz
Normal file
Binary file not shown.
|
|
@ -1,32 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 09:51:42 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(37): warning: start: implicit transition to `reject'
|
|
||||||
state start {
|
|
||||||
^^^^^
|
|
||||||
/opt/Xilinx/SDNet/2018.2/data/p4include/sume_switch.p4(40): error: Structure struct sume_metadata_t does not have a field unused
|
|
||||||
struct sume_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(39)
|
|
||||||
standard_metadata.unused = 0;
|
|
||||||
^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-095142-subparser-5.6.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-095142-subparser-5.6.xz
Normal file
Binary file not shown.
|
|
@ -1,35 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 09:52:11 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(37): warning: start: implicit transition to `reject'
|
|
||||||
state start {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(52): warning: realparser: unused instance
|
|
||||||
RealParser() realparser;
|
|
||||||
^^^^^^^^^^
|
|
||||||
minip4_solution.p4(45): error: parser TopParser: parser does not have a `start' state
|
|
||||||
parser TopParser(
|
|
||||||
^^^^^^^^^
|
|
||||||
minip4_solution.p4(45): warning: accept state in parser TopParser is unreachable
|
|
||||||
parser TopParser(
|
|
||||||
^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-095211-subparser-5.6.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-095211-subparser-5.6.xz
Normal file
Binary file not shown.
|
|
@ -1,74 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 09:53:26 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(37): warning: start: implicit transition to `reject'
|
|
||||||
state start {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(30): warning: accept state in parser RealParser is unreachable
|
|
||||||
parser RealParser(
|
|
||||||
^^^^^^^^^^
|
|
||||||
minip4_solution.p4(45): warning: accept state in parser TopParser is unreachable
|
|
||||||
parser TopParser(
|
|
||||||
^^^^^^^^^
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
./gen_testdata.py
|
|
||||||
Applying pkt on nf0 at 1:
|
|
||||||
Applying pkt on nf1 at 2:
|
|
||||||
Applying pkt on nf2 at 3:
|
|
||||||
Applying pkt on nf3 at 4:
|
|
||||||
nf0_applied times: [1]
|
|
||||||
nf1_applied times: [2]
|
|
||||||
nf2_applied times: [3]
|
|
||||||
nf3_applied times: [4]
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
|
|
||||||
Xilinx SDNet Compiler version 2018.2, build 2342300
|
|
||||||
|
|
||||||
Compilation successful
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_externs.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ ./testdata/ ./sw/ --base_address 0x44020000
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_API.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_P4_SWITCH_CLI.py src/.sdnet_switch_info.dat nf_sume_sdnet_ip/SimpleSumeSwitch/ sw/ /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/templates/ --base_address 0x44020000
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
|
|
||||||
cc -c -fPIC /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API/CAM.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
|
|
||||||
cc -std=c99 -Wall -Werror -fPIC -c libcam.c -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -I/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/API
|
|
||||||
cc -L/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/sw/sume -shared -o libcam.so libcam.o CAM.o -lsumereg
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/sw/CLI'
|
|
||||||
# The following command only applies if running P4_SWITCH Questa Simulation with Ubuntu
|
|
||||||
sed -i 's/vsim/vsim \-ldflags \"\-B\/usr\/lib\/x86\_64\-linux-gnu\"/g' nf_sume_sdnet_ip/SimpleSumeSwitch/questa.bash
|
|
||||||
# modify the P4_SWITCH_tb so that it writes the table configuration writes to a file
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/modify_P4_SWITCH_tb.py nf_sume_sdnet_ip/SimpleSumeSwitch/Testbench/SimpleSumeSwitch_tb.sv
|
|
||||||
# Fix introduced for SDNet 2017.4
|
|
||||||
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
|
|
||||||
sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
# Fix introduced for SDNet 2018.2
|
|
||||||
sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
|
|
||||||
cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
cp testdata/*.axi nf_sume_sdnet_ip/SimpleSumeSwitch/
|
|
||||||
+ date
|
|
||||||
Mit Jul 24 09:53:30 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch
|
|
||||||
+ ./vivado_sim.bash
|
|
||||||
+ find -name '*.v' -o -name '*.vp' -o -name '*.sv'
|
|
||||||
+ xargs -I % /opt/Xilinx/Vivado/2018.2/bin/xvlog -sv %
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-095326-subparser-5.6.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-095326-subparser-5.6.xz
Normal file
Binary file not shown.
File diff suppressed because it is too large
Load diff
BIN
netpfga/log/compile-2019-07-24-095730-subparser-5.6.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-095730-subparser-5.6.xz
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
BIN
netpfga/log/compile-2019-07-24-112325-toppipe-subcontrol.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-112325-toppipe-subcontrol.xz
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
BIN
netpfga/log/compile-2019-07-24-115200-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-115200-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,56 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 11:52:56 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(27): error: Could not find declaration for controller_debug
|
|
||||||
controller_debug;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(28): error: Could not find declaration for controller_reply
|
|
||||||
controller_reply;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(29): error: Could not find declaration for controller_debug_table_id
|
|
||||||
controller_debug_table_id;
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(32): error: Could not find declaration for ROUTING_TABLE_SIZE
|
|
||||||
size = ROUTING_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(34): error: Could not find declaration for controller_debug_table_id
|
|
||||||
default_action = controller_debug_table_id(TABLE_V6_NETWORKS);
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(44): error: Could not find declaration for controller_debug
|
|
||||||
controller_debug;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(45): error: Could not find declaration for controller_debug_table_id
|
|
||||||
controller_debug_table_id;
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(48): error: Could not find declaration for ROUTING_TABLE_SIZE
|
|
||||||
size = ROUTING_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(49): error: Could not find declaration for controller_debug_table_id
|
|
||||||
default_action = controller_debug_table_id(TABLE_V4_NETWORKS);
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(169): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(184): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-115256-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-115256-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,48 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 11:56:44 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
In file included from actions_egress.p4:30:0,
|
|
||||||
from actions_nat64_generic.p4:4,
|
|
||||||
from minip4_solution.p4:71:
|
|
||||||
actions_egress.p4:84:2: error: #endif without #if
|
|
||||||
#endif
|
|
||||||
^
|
|
||||||
In file included from actions_nat64_generic.p4:4:0,
|
|
||||||
from minip4_solution.p4:71:
|
|
||||||
actions_egress.p4:84:2: error: #endif without #if
|
|
||||||
#endif
|
|
||||||
^
|
|
||||||
actions_egress.p4(53): error: v6_networks: Duplicates declaration v6_networks
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(53)
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(70): error: v4_networks: Duplicates declaration v4_networks
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(70)
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
error: Preprocessor returned exit code 256; aborting compilation
|
|
||||||
error: 3 errors encountered, aborting compilation
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-115644-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-115644-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,35 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 11:57:31 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(62): error: Could not find declaration for ROUTING_TABLE_SIZE
|
|
||||||
size = ROUTING_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(78): error: Could not find declaration for ROUTING_TABLE_SIZE
|
|
||||||
size = ROUTING_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(169): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(184): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-115731-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-115731-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,719 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 11:58:11 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(6): error: Structure header Ethernet_h does not have a field dst_addr
|
|
||||||
header Ethernet_h {
|
|
||||||
^^^^^^^^^^
|
|
||||||
actions_egress.p4(17)
|
|
||||||
hdr.ethernet.dst_addr = mac_addr;
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field task
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(33)
|
|
||||||
meta.task = task;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field ingress_port
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(34)
|
|
||||||
meta.ingress_port = sume_metadata.src_port;
|
|
||||||
^^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field table_id
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(40)
|
|
||||||
meta.table_id = table_id;
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(54)
|
|
||||||
hdr.ipv6.dst_addr: lpm;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(71)
|
|
||||||
hdr.ipv4.dst_addr: lpm;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(9)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.src_addr[15:0]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(10)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.src_addr[31:16]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(11)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.dst_addr[15:0]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(12)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.dst_addr[31:16]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(14)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.totalLen -20; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(15)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.protocol; // 8 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(17)
|
|
||||||
meta.v4sum = ~tmp;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(23)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[15:0]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(24)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[31:16]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(25)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[47:32]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(26)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[63:48]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(27)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[79:64]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(28)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[95:80]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(29)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[111:96]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(30)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.src_addr[127:112]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(32)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[15:0]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(33)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[31:16]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(34)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[47:32]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(35)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[63:48]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(36)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[79:64]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(37)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[95:80]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(38)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[111:96]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(39)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.dst_addr[127:112]; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(41)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.payload_length; // 16 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(42)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv6.next_header; // 8 bit
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(44)
|
|
||||||
meta.v6sum = ~tmp;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field udp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(57)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(57)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(62)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v4sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field udp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(68)
|
|
||||||
hdr.udp.checksum = (bit<16>) tmp;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field udp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(75)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(75)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(80)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v6sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field udp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(86)
|
|
||||||
hdr.udp.checksum = (bit<16>) tmp;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field tcp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(93)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(93)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(98)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v4sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field tcp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(104)
|
|
||||||
hdr.tcp.checksum = (bit<16>) tmp;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field tcp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(111)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(111)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(116)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v6sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field tcp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(122)
|
|
||||||
hdr.tcp.checksum = (bit<16>) tmp;
|
|
||||||
^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(135)
|
|
||||||
shift_tmp = ( ((bit<16>) hdr.ipv4.version) << 12) +
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(136)
|
|
||||||
( ((bit<16>) hdr.ipv4.ihl) << 8) +
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(137)
|
|
||||||
( ((bit<16>) hdr.ipv4.diff_serv) << 2) +
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(138)
|
|
||||||
( (bit<16>) hdr.ipv4.ecn);
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(147)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.totalLen; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(149)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.identification; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(151)
|
|
||||||
shift_tmp = ((bit<16>) (hdr.ipv4.flags) << 13) +
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(152)
|
|
||||||
((bit<16>) hdr.ipv4.fragOffset);
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(158)
|
|
||||||
shift_tmp = ((bit<16>) (hdr.ipv4.ttl) << 8) +
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(159)
|
|
||||||
((bit<16>) hdr.ipv4.protocol);
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(165)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.src_addr[15:0]; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(166)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.src_addr[31:16]; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(167)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.dst_addr[15:0]; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(168)
|
|
||||||
tmp = tmp + (bit<16>) hdr.ipv4.dst_addr[31:16]; /* 16 bit */
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(170)
|
|
||||||
hdr.ipv4.checksum = ~tmp;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(12)
|
|
||||||
hdr.icmp.setValid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(13)
|
|
||||||
hdr.ipv4.protocol = PROTO_ICMP; // overwrite generic same protocol assumption
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field switch_task
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(16)
|
|
||||||
meta.switch_task = TASK_CHECKSUM_ICMP;
|
|
||||||
^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field chk_icmp
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(19)
|
|
||||||
meta.chk_icmp = 1;
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(21)
|
|
||||||
hdr.icmp6.setInvalid();
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp6_na_ns
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(24)
|
|
||||||
hdr.icmp6_na_ns.setInvalid();
|
|
||||||
^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp6_option_link_layer_addr
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(25)
|
|
||||||
hdr.icmp6_option_link_layer_addr.setInvalid();
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(30)
|
|
||||||
hdr.ipv4.setValid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(34)
|
|
||||||
hdr.ipv4.version = (bit<4>)4;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(35)
|
|
||||||
hdr.ipv4.ihl = (bit<4>)5; // internet header length: 4*5 = 20
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(39)
|
|
||||||
hdr.ipv4.diff_serv = (bit<6>)0; // no ToS
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(40)
|
|
||||||
hdr.ipv4.ecn = (bit<2>)0; // unsupported
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(41)
|
|
||||||
hdr.ipv4.totalLen = (bit<16>) hdr.ipv6.payload_length + 20; // ok under above constraints
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(41)
|
|
||||||
hdr.ipv4.totalLen = (bit<16>) hdr.ipv6.payload_length + 20; // ok under above constraints
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(42)
|
|
||||||
hdr.ipv4.identification = (bit<16>) 0; // no support for fragments
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(43)
|
|
||||||
hdr.ipv4.flags = (bit<3>) 0; // DF bit and more fragments
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(44)
|
|
||||||
hdr.ipv4.fragOffset = (bit<13>) 0; // 0 as there are no fragments
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(45)
|
|
||||||
hdr.ipv4.ttl = hdr.ipv6.hop_limit;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(45)
|
|
||||||
hdr.ipv4.ttl = hdr.ipv6.hop_limit;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(46)
|
|
||||||
hdr.ipv4.protocol = hdr.ipv6.next_header;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(46)
|
|
||||||
hdr.ipv4.protocol = hdr.ipv6.next_header;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(47)
|
|
||||||
hdr.ipv4.src_addr = src;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(48)
|
|
||||||
hdr.ipv4.dst_addr = dst;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(6): error: Structure header Ethernet_h does not have a field ethertype
|
|
||||||
header Ethernet_h {
|
|
||||||
^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(51)
|
|
||||||
hdr.ethernet.ethertype = TYPE_IPV4;
|
|
||||||
^^^^^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field chk_ipv4
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(56)
|
|
||||||
meta.chk_ipv4 = 1; /* need to calculate the hdrchecksum */
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(59)
|
|
||||||
hdr.ipv6.setInvalid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(64)
|
|
||||||
ipv6_addr_t src_offset = hdr.ipv6.src_addr - v6_src;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(67)
|
|
||||||
ipv4_addr_t dst = (ipv4_addr_t) (hdr.ipv6.dst_addr - nat64_prefix);
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(122)
|
|
||||||
hdr.icmp6.setValid();
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(123)
|
|
||||||
hdr.ipv6.next_header = PROTO_ICMP6;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field chk_icmp6
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(125)
|
|
||||||
meta.chk_icmp6 = 1;
|
|
||||||
^^^^^^^^^
|
|
||||||
minip4_solution.p4(18): error: Structure struct user_metadata_t does not have a field cast_length
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(126)
|
|
||||||
meta.cast_length = (bit<32>) hdr.ipv6.payload_length;
|
|
||||||
^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(126)
|
|
||||||
meta.cast_length = (bit<32>) hdr.ipv6.payload_length;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field icmp
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(128)
|
|
||||||
hdr.icmp.setInvalid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(133)
|
|
||||||
hdr.ipv6.setValid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(134)
|
|
||||||
hdr.ipv4.setInvalid();
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(6): error: Structure header Ethernet_h does not have a field ethertype
|
|
||||||
header Ethernet_h {
|
|
||||||
^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(136)
|
|
||||||
hdr.ethernet.ethertype = TYPE_IPV6;
|
|
||||||
^^^^^^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(138)
|
|
||||||
hdr.ipv6.dst_addr = dst;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(139)
|
|
||||||
hdr.ipv6.src_addr = src;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(140)
|
|
||||||
hdr.ipv6.version = (bit<4>) 6;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(141)
|
|
||||||
hdr.ipv6.traffic_class = (bit<8>) hdr.ipv4.diff_serv;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(141)
|
|
||||||
hdr.ipv6.traffic_class = (bit<8>) hdr.ipv4.diff_serv;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(142)
|
|
||||||
hdr.ipv6.flow_label = (bit<20>) 0;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(143)
|
|
||||||
hdr.ipv6.payload_length = (bit<16>) hdr.ipv4.totalLen - 20;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(143)
|
|
||||||
hdr.ipv6.payload_length = (bit<16>) hdr.ipv4.totalLen - 20;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(144)
|
|
||||||
hdr.ipv6.next_header = hdr.ipv4.protocol;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(144)
|
|
||||||
hdr.ipv6.next_header = hdr.ipv4.protocol;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(145)
|
|
||||||
hdr.ipv6.hop_limit = hdr.ipv4.ttl;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(145)
|
|
||||||
hdr.ipv6.hop_limit = hdr.ipv4.ttl;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(151)
|
|
||||||
ipv6_addr_t src = nat64_prefix + (ipv6_addr_t) hdr.ipv4.src_addr;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(153)
|
|
||||||
ipv4_addr_t dst_offset = hdr.ipv4.dst_addr - v4_dst;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv6
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(161)
|
|
||||||
hdr.ipv6.dst_addr: lpm;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(12): error: Structure struct Parsed_packet does not have a field ipv4
|
|
||||||
struct Parsed_packet {
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(176)
|
|
||||||
hdr.ipv4.dst_addr: lpm;
|
|
||||||
^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-115811-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-115811-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,33 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:02:07 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(12): error: Duplicate declaration of headers; previous at
|
|
||||||
typedef struct headers
|
|
||||||
^^^^^^^
|
|
||||||
headers.p4(201)
|
|
||||||
struct headers {
|
|
||||||
^^^^^^^
|
|
||||||
minip4_solution.p4(12):syntax error, unexpected IDENTIFIER, expecting {
|
|
||||||
typedef struct headers Parsed_packet
|
|
||||||
^^^^^^^^^^^^^
|
|
||||||
error: 2 errors encountered, aborting compilation
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120207-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-120207-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,27 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:03:11 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(36):syntax error, unexpected STRUCT
|
|
||||||
out struct
|
|
||||||
^^^^^^
|
|
||||||
error: 1 errors encountered, aborting compilation
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120311-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-120311-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,27 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:05:30 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(78):syntax error, unexpected IDENTIFIER "temp"
|
|
||||||
EthAddr_t temp
|
|
||||||
^^^^
|
|
||||||
error: 1 errors encountered, aborting compilation
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120530-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-120530-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,131 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:07:13 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field task
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(33)
|
|
||||||
meta.task = task;
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field ingress_port
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(34)
|
|
||||||
meta.ingress_port = sume_metadata.src_port;
|
|
||||||
^^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field table_id
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_egress.p4(40)
|
|
||||||
meta.table_id = table_id;
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(17)
|
|
||||||
meta.v4sum = ~tmp;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(44)
|
|
||||||
meta.v6sum = ~tmp;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(57)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(62)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v4sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(75)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.udp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(80)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v6sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(93)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v6sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(98)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v4sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v4sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(111)
|
|
||||||
bit<17> tmp = (bit<17>) hdr.tcp.checksum + (bit<17>) meta.v4sum;
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field v6sum
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_delta_checksum.p4(116)
|
|
||||||
tmp = tmp + (bit<17>) (0xffff - meta.v6sum);
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field switch_task
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(16)
|
|
||||||
meta.switch_task = TASK_CHECKSUM_ICMP;
|
|
||||||
^^^^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field chk_icmp
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(19)
|
|
||||||
meta.chk_icmp = 1;
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field chk_ipv4
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(56)
|
|
||||||
meta.chk_ipv4 = 1; /* need to calculate the hdrchecksum */
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field chk_icmp6
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(125)
|
|
||||||
meta.chk_icmp6 = 1;
|
|
||||||
^^^^^^^^^
|
|
||||||
minip4_solution.p4(22): error: Structure struct user_metadata_t does not have a field cast_length
|
|
||||||
struct user_metadata_t {
|
|
||||||
^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(126)
|
|
||||||
meta.cast_length = (bit<32>) hdr.ipv6.payload_length;
|
|
||||||
^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120713-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-120713-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,29 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:09:28 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
headers.p4(216): error: Structure struct metadata does not have a field unused
|
|
||||||
struct metadata {
|
|
||||||
^^^^^^^^
|
|
||||||
minip4_solution.p4(44)
|
|
||||||
meta.unused = 0;
|
|
||||||
^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120928-nat64actions-5.8.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-120928-nat64actions-5.8.xz
Normal file
Binary file not shown.
|
|
@ -1,55 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 12:09:46 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(52): warning: Table v6_networks is not used; removing
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(69): warning: Table v4_networks is not used; removing
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(159): warning: Table nat64 is not used; removing
|
|
||||||
table nat64 {
|
|
||||||
^^^^^
|
|
||||||
actions_nat64_generic.p4(174): warning: Table nat46 is not used; removing
|
|
||||||
table nat46 {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
|
|
||||||
out metadata meta,
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(35)
|
|
||||||
parser RealParser(
|
|
||||||
^^^^^^^^^^
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/p4_px_tables.py commands.txt .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
./gen_testdata.py
|
|
||||||
Applying pkt on nf0 at 1:
|
|
||||||
Applying pkt on nf1 at 2:
|
|
||||||
Applying pkt on nf2 at 3:
|
|
||||||
Applying pkt on nf3 at 4:
|
|
||||||
nf0_applied times: [1]
|
|
||||||
nf1_applied times: [2]
|
|
||||||
nf2_applied times: [3]
|
|
||||||
nf3_applied times: [4]
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
|
|
||||||
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_expect.axi --bus_width 256 dst.pcap
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
sdnet ./src/minip4.sdnet -skipEval -busType axi -busWidth 256 -singlecontrolport -workDir nf_sume_sdnet_ip -altVivadoScripts
|
|
||||||
Xilinx SDNet Compiler version 2018.2, build 2342300
|
|
||||||
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-120946-nat64actions-5.8.xz
Normal file
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netpfga/log/compile-2019-07-24-120946-nat64actions-5.8.xz
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Load diff
BIN
netpfga/log/compile-2019-07-24-121022-nat64actions-5.8.xz
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BIN
netpfga/log/compile-2019-07-24-121022-nat64actions-5.8.xz
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BIN
netpfga/log/compile-2019-07-24-131737-nat64apply-6.0.xz
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netpfga/log/compile-2019-07-24-131737-nat64apply-6.0.xz
Normal file
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|
|
@ -1,50 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 13:18:36 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(52): warning: Table v6_networks is not used; removing
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(69): warning: Table v4_networks is not used; removing
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(174): warning: Table nat46 is not used; removing
|
|
||||||
table nat46 {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
|
|
||||||
out metadata meta,
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(35)
|
|
||||||
parser RealParser(
|
|
||||||
^^^^^^^^^^
|
|
||||||
error: LPM table size should be 2^n - 1
|
|
||||||
actions_nat64_generic.p4(169): error: could not not map table size size
|
|
||||||
size = 64;
|
|
||||||
^^^^
|
|
||||||
error: table match_types are not the same
|
|
||||||
actions_arp.p4(35): error: could not map table key(s) KeyElement
|
|
||||||
hdr.arp.dst_ipv4_addr: lpm;
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
error: LPM table size should be 2^n - 1
|
|
||||||
actions_arp.p4(55): error: could not not map table size size
|
|
||||||
size = 64;
|
|
||||||
^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-131836-nat64apply-arp-6.1.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-131836-nat64apply-arp-6.1.xz
Normal file
Binary file not shown.
|
|
@ -1,29 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 13:21:23 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_nat64_generic.p4(169): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(184): error: Could not find declaration for NAT64_TABLE_SIZE
|
|
||||||
size = NAT64_TABLE_SIZE;
|
|
||||||
^^^^^^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-132123-nat64apply-arp-6.1.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-132123-nat64apply-arp-6.1.xz
Normal file
Binary file not shown.
|
|
@ -1,42 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 13:22:42 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(52): warning: Table v6_networks is not used; removing
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(69): warning: Table v4_networks is not used; removing
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(174): warning: Table nat46 is not used; removing
|
|
||||||
table nat46 {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
|
|
||||||
out metadata meta,
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(35)
|
|
||||||
parser RealParser(
|
|
||||||
^^^^^^^^^^
|
|
||||||
error: table match_types are not the same
|
|
||||||
actions_arp.p4(35): error: could not map table key(s) KeyElement
|
|
||||||
hdr.arp.dst_ipv4_addr: lpm;
|
|
||||||
^^^^^^^^^^^^^^^^^^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-132242-nat64apply-arp-6.1.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-132242-nat64apply-arp-6.1.xz
Normal file
Binary file not shown.
File diff suppressed because it is too large
Load diff
BIN
netpfga/log/compile-2019-07-24-222942-nat64apply-no-arp-6.2.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-222942-nat64apply-no-arp-6.2.xz
Normal file
Binary file not shown.
|
|
@ -1,44 +0,0 @@
|
||||||
+ date
|
|
||||||
Mit Jul 24 22:40:53 CEST 2019
|
|
||||||
+ cd /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
|
|
||||||
+ make
|
|
||||||
make -C src/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
rm -f *.sdnet *.tbl .sdnet_switch_info.dat
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
make -C testdata/ clean
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -f *.pcap *.txt *.pyc *.axi config_writes.* *_reg_defines.py
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
|
|
||||||
rm -rf nf_sume_sdnet_ip/
|
|
||||||
rm -f ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_24434.backup.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xelab.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimkernel.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/xsimcrash.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/xsc.log ./nf_sume_sdnet_ip/SimpleSumeSwitch/webtalk_24434.backup.jou ./nf_sume_sdnet_ip/SimpleSumeSwitch/xvlog.log
|
|
||||||
rm -f sw/config_tables.c
|
|
||||||
make -C src/
|
|
||||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
p4c-sdnet -o minip4.sdnet --sdnet_info .sdnet_switch_info.dat minip4_solution.p4
|
|
||||||
actions_egress.p4(52): warning: Table v6_networks is not used; removing
|
|
||||||
table v6_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_egress.p4(73): warning: Table v4_networks is not used; removing
|
|
||||||
table v4_networks {
|
|
||||||
^^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(178): warning: Table nat46 is not used; removing
|
|
||||||
table nat46 {
|
|
||||||
^^^^^
|
|
||||||
minip4_solution.p4(38): [--Wwarn=uninitialized_out_param] warning: out parameter meta may be uninitialized when RealParser terminates
|
|
||||||
out metadata meta,
|
|
||||||
^^^^
|
|
||||||
minip4_solution.p4(35)
|
|
||||||
parser RealParser(
|
|
||||||
^^^^^^^^^^
|
|
||||||
actions_nat64_generic.p4(173): error: table size too small for match_type(EM): 63 < 64
|
|
||||||
size = 63;
|
|
||||||
^^
|
|
||||||
actions_nat64_generic.p4(173): error: could not not map table size size
|
|
||||||
size = 63;
|
|
||||||
^^^^
|
|
||||||
Makefile:34: recipe for target 'all' failed
|
|
||||||
make[1]: *** [all] Error 1
|
|
||||||
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
|
|
||||||
Makefile:31: recipe for target 'frontend' failed
|
|
||||||
make: *** [frontend] Error 2
|
|
||||||
BIN
netpfga/log/compile-2019-07-24-224053-no-lpm-6.3.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-224053-no-lpm-6.3.xz
Normal file
Binary file not shown.
File diff suppressed because it is too large
Load diff
BIN
netpfga/log/compile-2019-07-24-224335-tablesize64-6.4.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-224335-tablesize64-6.4.xz
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
BIN
netpfga/log/compile-2019-07-24-224930-ipv6-ready-6.5.xz
Normal file
BIN
netpfga/log/compile-2019-07-24-224930-ipv6-ready-6.5.xz
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue