+notes -comment
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2 changed files with 42 additions and 18 deletions
23
doc/plan.org
23
doc/plan.org
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@ -5925,8 +5925,26 @@ nf3_applied times: []
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Should that not be [1] and then [3]?
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--------> same packet / object!!!!!!!!!!
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**** DONE try7: compile run output after ca. 1.5h
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CLOSED: [2019-07-21 Sun 16:38]
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#+BEGIN_CENTER
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/ip_repo'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
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WARNING: [IP_Flow 19-3664] IP 'bd_7ad4_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-26302-nsg-System/coregen/bd_7ad4_xpcs_0_1/elaborate/configure_gt.tcl'. Please regenerate to continue.
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WARNING: [IP_Flow 19-3664] IP 'bd_a1aa_xpcs_0' generated file not found '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/.Xil/Vivado-26302-nsg-System/coregen/bd_a1aa_xpcs_0_2/elaborate/configure_gt.tcl'. Please regenerate to continue.
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open_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1365.715 ; gain = 188.977 ; free physical = 9396 ; free virtual = 15104
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# puts "\nOpening $design Implementation design\n"
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Opening simple_sume_switch Implementation design
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# open_run impl_1
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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#+END_CENTER
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**** TODO try8: use new script generating different sequences/objects in gen_testdata
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*** TODO Further notes P4/master thesis
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- Cannot easily run P4 on notebook - changes to the system very
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invasive
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@ -5941,6 +5959,11 @@ nico@nsg-System:~/master-thesis/netpfga/log$ ls -alh /home/nico/projects/P4-Net
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ls: cannot access '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth/runme.log': No such file or directory
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- even "short" compile runs taking 30m+
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control_sub_m02_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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nico@nsg-System:~/master-thesis/netpfga/minip4/testdata$ less /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_m02_data_fifo_0_synth_1/runme.log: No such file or directory
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** The NetPFGA saga
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Problems encountered:
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- The logfile for a compile run is 10k+ lines
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37
netpfga/minip4/testdata/gen_testdata-port1.py
vendored
37
netpfga/minip4/testdata/gen_testdata-port1.py
vendored
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@ -1,10 +1,14 @@
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#!/usr/bin/env python
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# from switch_calc_headers import *
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from scapy.all import *
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from nf_sim_tools import *
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from collections import OrderedDict
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import sss_sdnet_tuples
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########################
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# pkt generation tools #
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########################
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pktsApplied = []
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pktsExpected = []
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@ -39,11 +43,11 @@ nf_id_map = {
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sss_sdnet_tuples.clear_tuple_files()
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def applyPkt(pkt, ingress, time):
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print("Applying pkt on {} at {}: ".format(ingress, time))
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pktsApplied.append(pkt)
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sss_sdnet_tuples.sume_tuple_in['src_port'] = nf_port_map[ingress]
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sss_sdnet_tuples.sume_tuple_expect['src_port'] = nf_port_map[ingress]
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pkt.time = time
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print("apply packet on {} at {}: {}".format(ingress, time, pkt.__repr__()))
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nf_applied[nf_id_map[ingress]].append(pkt)
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def expPkt(pkt, egress):
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@ -57,8 +61,6 @@ def expPkt(pkt, egress):
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nf_expected[1].append(pkt)
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nf_expected[2].append(pkt)
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nf_expected[3].append(pkt)
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print("exppkt packet on {}: {}".format(egress, pkt.__repr__()))
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def print_summary(pkts):
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for pkt in pkts:
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@ -76,6 +78,7 @@ def write_pcap_files():
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if (len(nf_expected[i]) > 0):
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wrpcap('nf{0}_expected.pcap'.format(i), nf_expected[i])
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# i = 0..3
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for i in nf_applied.keys():
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print "nf{0}_applied times: ".format(i), [p.time for p in nf_applied[i]]
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@ -101,24 +104,22 @@ lookup_table = {
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def test_port1():
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""" packets for a certain mac always go to nf0 """
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pktCnt = 0
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pktCnt = 1
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# First ethernet
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pktCnt += 1
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pkt = Ether(dst=MAC2, src=MAC1)
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pkt = pad_pkt(pkt, 64)
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applyPkt(pkt, 'nf0', pktCnt)
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for inport in [ 'nf0', 'nf1', 'nf2', 'nf3' ]:
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# Need to be regenerated, as object is modified above!
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pkt = Ether(dst=MAC2, src=MAC1)
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pkt = pad_pkt(pkt, 64)
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pktCnt += 1
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expPkt(pkt, 'nf0')
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# Send on nf0..nf3
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applyPkt(pkt, inport, pktCnt)
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pktCnt += 1
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applyPkt(pkt, 'nf1', pktCnt)
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# Always receive on nf0 - also regenerate here!
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pkt = Ether(dst=MAC2, src=MAC1)
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pkt = pad_pkt(pkt, 64)
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expPkt(pkt, 'nf0')
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pktCnt += 1
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expPkt(pkt, 'nf0')
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pktCnt += 1
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test_port1()
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# don't write at the moment, just help debugging
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# write_pcap_files()
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write_pcap_files()
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