80 lines
2.2 KiB
Coq
80 lines
2.2 KiB
Coq
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//-
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// Copyright (c) 2015 Noa Zilberman
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// All rights reserved.
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//
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// This software was developed by Stanford University and the University of Cambridge Computer Laboratory
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// under National Science Foundation under Grant No. CNS-0855268,
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// the University of Cambridge Computer Laboratory under EPSRC INTERNET Project EP/H040536/1 and
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// by the University of Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249 ("MRC2"),
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// as part of the DARPA MRC research programme.
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//
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// File:
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// axi_clocking.v
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//
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// Module:
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// axi_clocking
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//
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// Author: Noa Zilberman
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//
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// Description:
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// Sharable clocking resources for NetFPGA SUME
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//
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//
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// @NETFPGA_LICENSE_HEADER_START@
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//
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// Licensed to NetFPGA C.I.C. (NetFPGA) under one or more contributor
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// license agreements. See the NOTICE file distributed with this work for
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// additional information regarding copyright ownership. NetFPGA licenses this
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// file to you under the NetFPGA Hardware-Software License, Version 1.0 (the
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// "License"); you may not use this file except in compliance with the
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// License. You may obtain a copy of the License at:
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//
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// http://www.netfpga-cic.org
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//
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// Unless required by applicable law or agreed to in writing, Work distributed
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// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// @NETFPGA_LICENSE_HEADER_END@
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//
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`timescale 1ps / 1ps
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(* dont_touch = "yes" *)
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module axi_clocking
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(
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// Inputs
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input clk_in_p,
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input clk_in_n,
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input resetn,
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// Status outputs
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// IBUFDS 200MHz
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output locked,
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output clk_200
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);
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// Signal declarations
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wire s_axi_dcm_aclk0;
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wire clkfbout;
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// 200MHz differencial into single-rail
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IBUFDS clkin1_buf
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(.O (clkin1),
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.I (clk_in_p),
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.IB (clk_in_n)
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);
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clk_wiz_ip clk_wiz_i
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(
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// Clock in ports
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.clk_in1(clkin1), // input clk_in1
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// Clock out ports
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.clk_out1(clk_200), // output clk_out1
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// Status and control signals
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.resetn(resetn), // input resetn
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.locked(locked));
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endmodule
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