master-thesis/p4src/netpfga_dummy.p4

37 lines
624 B
Text
Raw Normal View History

2019-07-10 20:47:52 +00:00
#ifndef DUMMY_NETPFGA
#define DUMMY_NETPFGA
2019-07-17 15:41:54 +00:00
action send_to_port1() {
sume_metadata.dst_port = 1;
// sume_metadata.dst_port = 16;
2019-07-17 15:41:54 +00:00
}
2019-07-29 07:37:01 +00:00
action select_port_by_type() {
/*
>>> 0x86dd >> 11 v6
16
>>> 0x0800 >> 11 v4
1
>>> 0x0806 >> 11 ARP
1
*/
2019-07-29 07:40:20 +00:00
sume_metadata.dst_port = (bit<8>) (hdr.ethernet.ethertype >> 11);
2019-07-29 07:37:01 +00:00
}
2019-07-10 20:47:52 +00:00
table dummy_table_for_netpfga {
key = {
hdr.ethernet.ethertype: exact;
2019-07-10 20:47:52 +00:00
}
actions = {
send_to_port1;
2019-07-29 07:37:01 +00:00
select_port_by_type;
set_egress_port;
2019-07-10 20:47:52 +00:00
}
size = 64;
2019-07-29 07:37:01 +00:00
default_action = select_port_by_type; //send_to_port1;
2019-07-10 20:47:52 +00:00
}
#endif