Adding logs from plan.org
This commit is contained in:
Nico Schottelius
parent
695f4ed94c
commit
06e963e606
6 changed files with 291 additions and 36 deletions
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@ -103,10 +103,13 @@ the two protocols for this thesis are:
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\label{fig:ipv4header}
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\end{figure}
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% ----------------------------------------------------------------------
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\section{\label{background:arpndp}ARP and NDP - FIXME}
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\section{\label{background:arpndp}ARP and NDP, ICMP ICMP6- FIXME}
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Required for finding host.
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ARP who has
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NDP similar -- add traces here
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being able to answer to error messages
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MTU / pmtu
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% ----------------------------------------------------------------------
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\section{\label{background:transition}IPv6 Translation Mechanisms}
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While in this thesis the focus was in NAT64 as a translation mechanism,
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@ -14,7 +14,7 @@ Many misleading
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\section{\label{conclusion:bmv2}BMV2}
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maybe remove
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\section{\label{conclusion:P4}P4}
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@ -39,6 +39,18 @@ ternary matching.
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switch cannot be used in actions
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if things don't work, often a checksum problem.
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if frame checksum, then length of packet is broken
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\begin{verbatim}
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p4c --target bmv2 --arch v1model --std p4-16 "../p4src/static-mapping.p4" -o "/home/p4/master-thesis/p4src"
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../p4src/static-mapping.p4(366): error: Program is not supported by this target, because table MyIngress.v6_networks has multiple successors
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table v6_networks {
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^^^^^^^^^^^
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\end{verbatim}
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\begin{verbatim}
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ipaddress.ip_network("2001:db8:61::/64")
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IPv6Network(u'3230:3031:3a64:6238:3a36:313a:3a2f:3634/128')
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@ -59,6 +71,8 @@ Hitting expression bug
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\section{\label{conclusion:netpfga}NetFGPA - all HERE}
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personal note here
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MTU limitations: 1500 according to a private mail from Salvator Galea
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cambridge / uk
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long compile process
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error prone compile process
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@ -69,6 +83,29 @@ Vivado
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SDNET
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xx k lines of supporting code
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Vivado installation: silent errors, infinite loop, missing libncurses5
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82k lines of code that are interdependent
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Many non critical error messages on the way
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Zero exit fatal errors
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missing / spreaded documentation
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tcpdump on local nfX doesn't work -> can only debug on other endpoint
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First card: Writing tables fails
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hardware debug shows some errors
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but hardware debug on correct card also shows some error
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Debug ioctl errors when writing table entries
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Output all ports -> port mapping documented only in a testdata script
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hwtest: Execution fails due to missing djtgcfg
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no payload accessq
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Many workarounds
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@ -91,6 +128,11 @@ Renaming VARIABLES in the definition of
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Reproducibility:
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hours for finding right output ports
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packet size / annotation
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\section{\label{conclusion:realworld}Real world applications}
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Can be deployed using the netpfga. Or Barefoot or Arista.
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@ -106,7 +148,24 @@ Different HW
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Speed only limited to line speed. Could be running at 100 Gbit/s
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without modifications.
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\section{todo}
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PMTU
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handling error cases
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Our algorithm uses the IPv4-Compatible IPv6 Address\cite{rfc4291} to
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embed IPv4 addresses. However RFC6052\cite{rfc6052} defines different
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embeddings depending on the prefix size. A future version should
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support these schemes to be compatible to other implementations.
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No fragmentation
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No address / mac learning
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\section{\label{conclusion:closing}Closing words (NAME?)}
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While the port to NetPFGA was significantly more effort then expected,
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the learnings of the different layers were very much appreciated / liked
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It was a
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\section{todo - FIXME: remove}
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\begin{verbatim}
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***** Summary eher kurz
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***** Outlook als subsection!
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@ -147,3 +147,4 @@ not the full headers are used, but the pseudo headers (compare figures
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\ref{fig:ipv6pseudoheader} and \ref{fig:ipv4pseudoheader}).
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To compensate the carry bit, our code uses 17 bit integers for
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correcting the carry.
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% FIXME: add note to python script / checksum diffing
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@ -12,7 +12,7 @@ NetFPGA: capabale of line speed Nat64, focused port on nat64
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\section{\label{Results:BMV2}BMV2}
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Responds to icmp, icmp6
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ndp
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ndp \cite{rfc4861}
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arp
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test framework openvswitch
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@ -20,6 +20,14 @@ test framework openvswitch
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Fully functional host
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Can compute checksums on its own.
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focus on typical use cases of icmp, icmp6, the software implementation
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supports translating echo request and echo reply messages, but does
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not support all ICMP/ICMP6 translations that are defined in
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RFC6145\cite{rfc6145}.
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Stateful : no automatic removal
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\section{\label{results:tayga}Tayga}
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3gbit
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@ -41,7 +49,17 @@ General result: limited NAT64 is working, however
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\section{\label{results:softwarenat64}NAT64 in Software}
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Tayga, Jool
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\section{todo}
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\section{\label{results:features}Feature comparison}
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speed - sessions - eamt
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can act as host
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lpm tables
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ping
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ping6 support
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ndp
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controller support
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\section{todo - FIXME: remove}
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\begin{verbatim}
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***** Dorth eher detailiertes Drawing
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175
doc/appendix.tex
175
doc/appendix.tex
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@ -1497,6 +1497,181 @@ root@ESPRIMO-P956:~#
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\chapter{\label{bufferssssss}Buffer}
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\section{NetFPGA compile errors}
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- infinite loop in installer
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\begin{verbatim}
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# Fix introduced for SDNet 2017.4
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim.bash
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sed -i 's/xsim\.dir\/xsc\/dpi\.so/dpi\.so/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp: cannot stat 'src/*.tbl': No such file or directory
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make: *** [Makefile:23: cpp_test] Error 1
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[23:12] loch:minip4%
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\end{verbatim}
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\begin{verbatim}
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ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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\end{verbatim}
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\begin{verbatim}
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/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang -fPIC -c -std=gnu89 -nobuiltininc -nostdinc++ -w -Wl,--unres
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olved-symbols=ignore-in-object-files -fbracket-depth=1048576 -I/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/../li
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b/clang/3.1/include -fPIC -m64 -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/ob
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j/xsim_3.c" -O0 -sim -o "xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.lnx64.o" -DXILINX_SIMULATOR
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/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot
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open shared object file: No such file or directory
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ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_tb#work.glbl/obj/xsim_3.c.
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ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
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[20:00] rainbow:SimpleSumeSwitch%
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\end{verbatim}
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\begin{verbatim}
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# Fix introduced for SDNet 2018.2
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sed -i 's/glbl_sim/glbl/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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sed -i 's/SimpleSumeSwitch_tb_sim#work.glbl/SimpleSumeSwitch_tb/g' nf_sume_sdnet_ip/SimpleSumeSwitch/vivado_sim_waveform.bash
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cp src/*.tbl nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp testdata/*.txt nf_sume_sdnet_ip/SimpleSumeSwitch/
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cp: cannot stat 'testdata/*.txt': No such file or directory
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make: *** [Makefile:17: all] Error 1
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[15:46] rainbow:minip4%
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\end{verbatim}
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\begin{verbatim}
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make -C testdata/
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make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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./gen_testdata.py
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_in.axi --bus_width 256 src.pcap
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 108, in <module>
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write_to_file(args.file_pcap, args.output)
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 88, in write_to_file
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for pkt in rdpcap(file_in):
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 728, in rdpcap
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with PcapReader(filename) as fdesc:
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 751, in __call__
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filename, fdesc, magic = cls.open(filename)
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File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 778, in open
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fdesc = open(filename, "rb")
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IOError: [Errno 2] No such file or directory: 'src.pcap'
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make[1]: *** [Makefile:5: all] Error 1
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
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make: *** [Makefile:32: frontend] Error 2
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[15:47] rainbow:minip4%
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\end{verbatim}
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\begin{verbatim}
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update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
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al = 21975 ; free virtual = 33161
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loading libsume..
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
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fault/run.py", line 42, in <module>
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import config_writes
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_de
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fault/config_writes.py", line 7
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^
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IndentationError: expected an indented block
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while executing
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"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
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invoked from within
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"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_s
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ume_switch_sim.tcl" line 177)
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:21:21 2019...
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\end{verbatim}
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\begin{verbatim}
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_stim.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_expected.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.log': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_expect.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/reg_stim.axi': No such file or directory
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
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\end{verbatim}
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\begin{verbatim}
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# add_wave $nf_sume_sdnet_ip/out_src_port
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# add_wave $nf_sume_sdnet_ip/out_dst_port
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# set const_reg_ip /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
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# add_wave_divider {const reg extern signals}
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# add_wave $const_reg_ip
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ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /top_tb/top_sim/nf_datapath_0/nf_sume_sdnet_wrapper_1/inst/SimpleSumeSwitch_inst/const_reg_rw_0/
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ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
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while executing
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"add_wave $const_reg_ip "
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 328)
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INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:31:59 2019...
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make: *** [Makefile:121: sim] Error 1
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
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512
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=== Work directory is /tmp/nico/test/simple_sume_switch
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=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_0_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_1_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_2_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/nf_interface_3_log.axi': No such file or directory
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
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[15:31] rainbow:P4-NetFPGA%
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\end{verbatim}
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\begin{verbatim}
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# open_run impl_1
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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\end{verbatim}
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\begin{verbatim}
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ERROR: [BD 41-171] The modes of the interface pins 'cfg_interrupt'(Slave) and 'pcie3_cfg_interrupt'(Slave) are incompatible. They cannot be connected.
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ERROR: [BD 5-3] Error: running connect_bd_intf_net.
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ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
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while executing
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"connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt [get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins pcie3_7x_1/pcie3_cf..."
|
||||
(procedure "create_hier_cell_dma_sub" line 141)
|
||||
invoked from within
|
||||
"create_hier_cell_dma_sub [current_bd_instance .] dma_sub"
|
||||
(procedure "create_root_design" line 68)
|
||||
invoked from within
|
||||
"create_root_design """
|
||||
(file "./tcl/control_sub.tcl" line 729)
|
||||
|
||||
while executing
|
||||
"source ./tcl/control_sub.tcl"
|
||||
(file "tcl/simple_sume_switch.tcl" line 89)
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
\section{Traces}
|
||||
|
||||
Proof of stuff working, reference for each stage / feature
|
||||
|
||||
Stuff that needs to be cleaned up
|
||||
|
||||
\section{Introduction}
|
||||
|
|
|
|||
61
doc/plan.org
61
doc/plan.org
|
|
@ -1,4 +1,5 @@
|
|||
* Time table / log
|
||||
* DONE Time table / log
|
||||
CLOSED: [2019-08-12 Mon 17:01]
|
||||
| When? | What? | Notes |
|
||||
| 2019-02-21 | Kick-Off | x |
|
||||
| | Finish all admin points | x |
|
||||
|
|
@ -244,14 +245,14 @@
|
|||
| | * RFC4291 IPv4-Mapped IPv6 Address (16 1s) | |
|
||||
| | | |
|
||||
| | - Session handling | |
|
||||
| | * RFC6145: Translation ip/icmp, obsoleted by RFC 7915 | |
|
||||
| | * RFC6145: Translation ip/icmp, obsoleted by RFC 7915 | x |
|
||||
| | * RFC6146: NAT64 definition, only TCP, UDP, and ICMP traffic | |
|
||||
| | * RFC6052: embedding support | |
|
||||
| | * Mode: IPv6 outgoing -> "masquarading" | |
|
||||
| | * Mode: IPv4 | |
|
||||
| | | |
|
||||
| | - Translation details | |
|
||||
| | * How to handle ICMP4->icmp6 correctly (RFC7915) | |
|
||||
| | * How to handle ICMP4->icmp6 correctly (RFC7915) | x |
|
||||
| | | |
|
||||
| | - Hardware | |
|
||||
| | * NetFPGA | |
|
||||
|
|
@ -266,7 +267,7 @@
|
|||
| | | |
|
||||
| | | |
|
||||
| | Meeting notes | |
|
||||
| | - difference based | |
|
||||
| | - difference based | x |
|
||||
| | - first physical access | |
|
||||
| | - tofino: if it compiles -> line rate | |
|
||||
| | - chaining switches / OS -> single port rate | |
|
||||
|
|
@ -294,21 +295,21 @@
|
|||
| | Bidirectional support | |
|
||||
| | Will need IPv6 embedding suport https://tools.ietf.org/html/rfc6052 | |
|
||||
| | | |
|
||||
| 2019-04-18 | NAT64 prefix based IPv6->IPv4 conversion [tayga] | |
|
||||
| 2019-04-18 | NAT64 prefix based IPv6->IPv4 conversion [tayga] | x |
|
||||
| | Use case: IPv6 hosts send to specific /96 | |
|
||||
| | | |
|
||||
| 2019-05-23 | NAT64 dynamic pool implementation: n:1 ipv6 to ipv4 mapping | |
|
||||
| | And n:1 stateful mappings https://www.jool.mx/en/run-nat64.html | |
|
||||
| | Needs active controller | |
|
||||
| | Needs timeout / leases | |
|
||||
| 2019-05-23 | NAT64 dynamic pool implementation: n:1 ipv6 to ipv4 mapping | x |
|
||||
| | And n:1 stateful mappings https://www.jool.mx/en/run-nat64.html | x |
|
||||
| | Needs active controller | x |
|
||||
| | Needs timeout / leases | x |
|
||||
| | Might work w/ registers | |
|
||||
| | | |
|
||||
| 2019-06-16 | | |
|
||||
| | Laurent meeting | |
|
||||
| | | |
|
||||
| | - Vivado installation: silent errors, infinite loop, missing libncurses5 | |
|
||||
| | - Vivado installation: silent errors, infinite loop, missing libncurses5 | x |
|
||||
| | | |
|
||||
| | - Compiling netfpga: 82k lines of code that are interdependent | |
|
||||
| | - Compiling netfpga: 82k lines of code that are interdependent | x |
|
||||
| | - Many non critical error messages on the way | |
|
||||
| | - Zero exit fatal errors | |
|
||||
| | | |
|
||||
|
|
@ -324,28 +325,28 @@
|
|||
| | | |
|
||||
| | - HW test | |
|
||||
| | * compiling for 3 days | |
|
||||
| | * Execution fails due to missing djtgcfg | |
|
||||
| | * Execution fails due to missing djtgcfg | x |
|
||||
| | | |
|
||||
| | Payload to control plane | |
|
||||
| | - digest not possible due to missing | |
|
||||
| | - digest not possible due to missing content | |
|
||||
| | - might work with working | |
|
||||
| | | |
|
||||
| | Next steps: | |
|
||||
| | - Debug ioctl errors when writing table entries | |
|
||||
| | - Debug ioctl errors when writing table entries | x |
|
||||
| | | |
|
||||
| | - Understand HDL or PX user engines for writing checksum part | |
|
||||
| | - Understand HDL or PX user engines for writing checksum part | x |
|
||||
| | - Adjust controller to digest | |
|
||||
| | | |
|
||||
| | HDL notes | |
|
||||
| | - cycle limitations | |
|
||||
| | - variable length might be a problem | |
|
||||
| | - variable length might be a problem | x |
|
||||
| | | |
|
||||
| | Next steps after discussion: | |
|
||||
| | | |
|
||||
| | - checkout ipv6 test on netpfga / modify v6 packet | |
|
||||
| | - checkout whether diff is possible on checksum -> see ttl | |
|
||||
| | - checkout whether diff is possible on checksum -> see ttl | x |
|
||||
| | - checkout externs of Hendrik / report | |
|
||||
| | - Asses checksum difficulty | |
|
||||
| | - Asses checksum difficulty | x |
|
||||
| | | |
|
||||
| | Handing in thesis: | |
|
||||
| | | |
|
||||
|
|
@ -371,9 +372,9 @@
|
|||
| | - overflow (delta > payload) handling unclear | |
|
||||
| | | |
|
||||
| | Netpfga | |
|
||||
| | - Old one had several failure messages (one in DDR area) | |
|
||||
| | - New one: tables can be written | |
|
||||
| | - Need 3 ports: v4, v6, management | |
|
||||
| | - Old one had several failure messages (one in DDR area) | x |
|
||||
| | - New one: tables can be written | x |
|
||||
| | - Need 3 ports: v4, v6, management | x |
|
||||
| | | |
|
||||
| | Next steps: | |
|
||||
| | - Test checksums delta on software switch | |
|
||||
|
|
@ -390,17 +391,17 @@
|
|||
| 2019-07-01 | | |
|
||||
| | Meeting Laurent | |
|
||||
| | | |
|
||||
| | - Diff'ing in python: | |
|
||||
| | - Diff'ing in python: | x |
|
||||
| | * offsetting works | |
|
||||
| | * Need to adjust to actual translation code | |
|
||||
| | | |
|
||||
| | - Phasing in netpfga code / copy & compile & fix | |
|
||||
| | * Code structure w/o apply logic | |
|
||||
| | * DIFF: Output port selection | |
|
||||
| | * DIFF: Output port selection | x |
|
||||
| | * DIFF: Sending to CPU | |
|
||||
| | | |
|
||||
| | - Diff'ing in P4 | |
|
||||
| | * IPv4 checksum is w/o payload | |
|
||||
| | * IPv4 checksum is w/o payload | x |
|
||||
| | | |
|
||||
| | - Different generated output | |
|
||||
| | | |
|
||||
|
|
@ -419,7 +420,7 @@
|
|||
| | - Maybe compile to openvswitch | |
|
||||
| | | |
|
||||
| 2019-07-06 | | |
|
||||
| | Test case for delta in P4/BMV2: | |
|
||||
| | Test case for delta in P4/BMV2: | x |
|
||||
| | | |
|
||||
| | | |
|
||||
| | | |
|
||||
|
|
@ -427,7 +428,7 @@
|
|||
| 2019-07-11 | | |
|
||||
| | Meeting Laurent | |
|
||||
| | | |
|
||||
| | - Delta diff in P4 from v4 -> v6: checksum working, off by one error | |
|
||||
| | - Delta diff in P4 from v4 -> v6: checksum working, off by one error | x |
|
||||
| | -> assume overflow | |
|
||||
| | -> very likely | |
|
||||
| | | |
|
||||
|
|
@ -443,7 +444,7 @@
|
|||
| | https://github.com/jkitchin/org-ref | |
|
||||
| | | |
|
||||
| | | |
|
||||
| 2019-07-25 | Benmarking results between P4, Jool, Tayga | |
|
||||
| 2019-07-25 | Benmarking results between P4, Jool, Tayga | x |
|
||||
| | Real hardware of advantage | |
|
||||
| | | |
|
||||
| | | |
|
||||
|
|
@ -604,7 +605,6 @@ DEBUG:main:cpu = <CpuHeader task=DEBUG ingress_port=1 type=0x86dd |<Raw load='
|
|||
DEBUG:main:o=<Ether dst=33:33:ff:00:00:42 src=00:00:0a:00:00:01 type=0x86dd |<IPv6 version=6 tc=0 fl=0 plen=32 nh=ICMPv6 hlim=255 src=2001:db8::1 dst=ff02::1:ff00:42 |<ICMPv6ND_NS type=Neighbor Solicitation code=0 cksum=0xd3a4 res=0 tgt=2001:db8::42 |<ICMPv6NDOptSrcLLAddr type=1 len=1 lladdr=00:00:0a:00:00:01 |>>>>
|
||||
DEBUG:main:Debug purpose only
|
||||
***** Disable debug by default -> gives correct packets
|
||||
|
||||
DEBUG:main:INCOMING: <Ether dst=33:33:ff:00:00:42 src=00:00:0a:00:00:01 type=0x4242 |<Raw load='\x00\x01\x00\x01\x86\xdd`\x00\x00\x00\x00 :\xff \x01\r\xb8\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xff\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xff\x00\x00B\x87\x00\xd3\xa4\x00\x00\x00\x00 \x01\r\xb8\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00B\x01\x01\x00\x00\n\x00\x00\x01' |>>
|
||||
DEBUG:main:cpu = <CpuHeader task=ICMP6_NS ingress_port=1 type=0x86dd |<Raw load='`\x00\x00\x00\x00 :\xff \x01\r\xb8\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xff\x02\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xff\x00\x00B\x87\x00\xd3\xa4\x00\x00\x00\x00 \x01\r\xb8\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00B\x01\x01\x00\x00\n\x00\x00\x01' |>>
|
||||
DEBUG:main:o=<Ether dst=33:33:ff:00:00:42 src=00:00:0a:00:00:01 type=0x86dd |<IPv6 version=6 tc=0 fl=0 plen=32 nh=ICMPv6 hlim=255 src=2001:db8::1 dst=ff02::1:ff00:42 |<ICMPv6ND_NS type=Neighbor Solicitation code=0 cksum=0xd3a4 res=0 tgt=2001:db8::42 |<ICMPv6NDOptSrcLLAddr type=1 len=1 lladdr=00:00:0a:00:00:01 |>>>>
|
||||
|
|
@ -630,7 +630,6 @@ multicast address of the target address."
|
|||
****** create a multicast group with an ID
|
||||
****** associate the "node" with the multicast group ID
|
||||
**** If destination is within ff02::1:ff00:0/104, multicast
|
||||
|
||||
*** DONE Make switch answer icmp6 echo request for
|
||||
*** DONE Introduce mixed mode: switch: icmp6 echo reply, controller: NDP
|
||||
**** DONE try 1: reply seen, but checksum is incorrect
|
||||
|
|
@ -1561,7 +1560,8 @@ Cannot find required executable simple_switch.
|
|||
Please make sure that it is installed and available in your $PATH:
|
||||
(/home/nico/vcs/master-thesis/support/virtualenv-with-site/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/home/nico/vcs/master-thesis/support/p4c/build/)
|
||||
(virtualenv-with-site) root@line:/home/nico/vcs/master-thesis/p4app#
|
||||
** TODO Port to Hardware
|
||||
** DONE Port to Hardware
|
||||
CLOSED: [2019-08-12 Mon 17:29]
|
||||
*** NetPFGA documentation
|
||||
**** Port mapping
|
||||
| 1 | nf0 |
|
||||
|
|
@ -1570,7 +1570,6 @@ Please make sure that it is installed and available in your $PATH:
|
|||
**** DONE Understand the simulations part -> not atm
|
||||
**** DONE Install vivado
|
||||
**** DONE Install SDNET
|
||||
|
||||
**** DONE fix license issue
|
||||
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/switch_calc/testdata'
|
||||
echo ok
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue