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Merge branch 'master' of gitlab.ethz.ch:nicosc/master-thesis

This commit is contained in:
Nico Schottelius 2019-07-23 23:49:57 +02:00
parent 796e9f383d 7ab4510c36
commit 569868cdae
6 changed files with 28642 additions and 159 deletions
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p4src/minip4_solution-mirror.p4
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@ -2,10 +2,6 @@
#include <sume_switch.p4> #include <sume_switch.p4>
#include "headers.p4" #include "headers.p4"
/********************************************************************************
* Header
*/
typedef bit<48> EthAddr_t; typedef bit<48> EthAddr_t;
header Ethernet_h { header Ethernet_h {
EthAddr_t dstAddr; EthAddr_t dstAddr;
@ -28,17 +24,18 @@ struct digest_data_t {
bit<256> unused; bit<256> unused;
} }
/******************************************************************************** /********************************************************************************
* Parser * Parser
*/ */
@Xilinx_MaxPacketRegion(1024) @Xilinx_MaxPacketRegion(1024)
parser TopParser(packet_in b, parser TopParser(
out Parsed_packet p, packet_in b,
out user_metadata_t user_metadata, out Parsed_packet p,
out digest_data_t digest_data, out user_metadata_t user_metadata,
inout sume_metadata_t sume_metadata) { out digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
state start { state start {
b.extract(p.ethernet); b.extract(p.ethernet);
user_metadata.unused = 0; user_metadata.unused = 0;
@ -51,10 +48,11 @@ parser TopParser(packet_in b,
/******************************************************************************** /********************************************************************************
* Main * Main
*/ */
control TopPipe(inout Parsed_packet p, control TopPipe(
inout user_metadata_t user_metadata, inout Parsed_packet p,
inout digest_data_t digest_data, inout user_metadata_t user_metadata,
inout sume_metadata_t sume_metadata) { inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
action swap_eth_addresses() { action swap_eth_addresses() {
EthAddr_t temp = p.ethernet.dstAddr; EthAddr_t temp = p.ethernet.dstAddr;
@ -97,9 +95,7 @@ control TopPipe(inout Parsed_packet p,
send_to_all_ports; send_to_all_ports;
} }
size = 64; size = 64;
// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
default_action = send_to_port1; // test_port1() default_action = send_to_port1; // test_port1()
// default_action = send_to_all_ports; // test_allports():
} }
apply { apply {
@ -112,11 +108,13 @@ control TopPipe(inout Parsed_packet p,
*/ */
@Xilinx_MaxPacketRegion(1024) @Xilinx_MaxPacketRegion(1024)
control TopDeparser(packet_out b, control TopDeparser(
in Parsed_packet p, packet_out b,
in user_metadata_t user_metadata, in Parsed_packet p,
inout digest_data_t digest_data, in user_metadata_t user_metadata,
inout sume_metadata_t sume_metadata) { inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
apply { apply {
b.emit(p.ethernet); b.emit(p.ethernet);
} }

246
p4src/minip4_solution.p4
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@ -2,20 +2,10 @@
#include <sume_switch.p4> #include <sume_switch.p4>
#include "headers.p4" #include "headers.p4"
/********************************************************************************
* Features
*/
// #define ENABLE_CONTROLLER 1
/********************************************************************************
* Header
*/
typedef bit<48> EthAddr_t; typedef bit<48> EthAddr_t;
header Ethernet_h { header Ethernet_h {
EthAddr_t dstAddr; EthAddr_t dst_addr;
EthAddr_t srcAddr; EthAddr_t src_addr;
bit<16> etherType; bit<16> etherType;
} }
@ -34,54 +24,124 @@ struct digest_data_t {
bit<256> unused; bit<256> unused;
} }
/******************************************************************************** /********************************************************************************
* Parser * Parser
*/ */
// @Xilinx_MaxPacketRegion(1024)
// parser TopParser(packet_in b,
// out Parsed_packet p,
// out user_metadata_t user_metadata,
// out digest_data_t digest_data,
// inout sume_metadata_t sume_metadata) {
// }
@Xilinx_MaxPacketRegion(1024) @Xilinx_MaxPacketRegion(1024)
parser TopParser(packet_in packet, parser TopParser(
out headers hdr, packet_in packet,
out metadata meta, out Parsed_packet hdr,
// out user_metadata_t user_metadata, out user_metadata_t user_metadata,
out digest_data_t digest_data, out digest_data_t digest_data,
inout sume_metadata_t standard_metadata) { inout sume_metadata_t standard_metadata) {
state start { state start {
packet.extract(hdr.ethernet); packet.extract(hdr.ethernet);
//user_metadata.unused = 0; user_metadata.unused = 0;
meta.task = 0; // all others missing
digest_data.unused = 0; digest_data.unused = 0;
transition accept; transition accept;
} }
// #include "parsers.p4"
} }
/******************************************************************************** /********************************************************************************
* Main * Main
*/ */
control TopPipe(
inout Parsed_packet hdr,
inout user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
// control TopPipe(inout Parsed_packet p, action swap_eth_addresses() {
EthAddr_t temp = hdr.ethernet.dst_addr;
hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
hdr.ethernet.src_addr = temp;
// inout digest_data_t digest_data, /* set egress port */
// inout sume_metadata_t sume_metadata) { sume_metadata.dst_port = sume_metadata.src_port;
}
action send_to_port1() {
sume_metadata.dst_port = 1;
}
action send_to_all_ports() {
/* Taken from commands.txt of the "int" project:
table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101
python convert:
>>> 0b01010101
85
*/
sume_metadata.dst_port = 85;
}
action do_nothing() {
EthAddr_t temp = hdr.ethernet.dst_addr;
}
table lookup_table {
key = {
hdr.ethernet.dst_addr: exact;
}
actions = {
swap_eth_addresses;
do_nothing;
send_to_port1;
send_to_all_ports;
}
size = 64;
default_action = send_to_port1; // test_port1()
}
apply {
lookup_table.apply();
}
}
/********************************************************************************
* Deparser
*/
@Xilinx_MaxPacketRegion(1024)
control TopDeparser(
packet_out packet,
in Parsed_packet hdr,
in user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
apply {
packet.emit(hdr.ethernet);
}
}
/********************************************************************************
* Switch
*/
SimpleSumeSwitch(
TopParser(),
TopPipe(),
TopDeparser()
) main;
// in headers hdr,
//in metadata meta,
// out headers hdr,
// out metadata meta,
//meta.task = 0; // all others missing
// #include "parsers.p4"
// inout headers hdr,
//inout metadata meta,
control TopPipe(inout headers hdr,
inout metadata meta,
//inout user_metadata_t user_metadata,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
// actions to be enabled // actions to be enabled
// #include "actions_nat64_generic.p4" // includes controller & delta checksum // #include "actions_nat64_generic.p4" // includes controller & delta checksum
@ -91,7 +151,6 @@ control TopPipe(inout headers hdr,
// #include "actions_delta_checksum.p4" // non payload based checksumming // #include "actions_delta_checksum.p4" // non payload based checksumming
// apply { // apply {
// if(hdr.ipv6.isValid()) { // if(hdr.ipv6.isValid()) {
// if(nat64.apply().hit) { /* generic / static nat64 done */ // if(nat64.apply().hit) { /* generic / static nat64 done */
@ -173,105 +232,16 @@ control TopPipe(inout headers hdr,
// } // }
action swap_eth_addresses() {
EthAddr_t temp = hdr.ethernet.dst_addr;
hdr.ethernet.dst_addr = hdr.ethernet.src_addr;
hdr.ethernet.src_addr = temp;
/* set egress port */
sume_metadata.dst_port = sume_metadata.src_port;
}
action send_to_port1() {
sume_metadata.dst_port = 1;
}
// action send_testdata_to_port1() { // action send_testdata_to_port1() {
// // python: MAC2 = "08:22:22:22:22:08" // // python: MAC2 = "08:22:22:22:22:08"
// if(hdr.ethernet.dst_addr == 0x082222222208) { // if(hdr.ethernet.dst_addr == 0x082222222208) {
// sume_metadata.dst_port = 1; // sume_metadata.dst_port = 1;
// } // }
// } // }
//#ifdef ENABLE_CONTROLLER
action send_to_all_ports() { // #include "actions_controller.p4"
/* Taken from commands.txt of the "int" project: //#endif
table_cam_add_entry forward set_output_port 0xffffffffffff => 0b01010101 // #ifdef ENABLE_CONTROLLER
// controller_debug;
python convert: // #endif
>>> 0b01010101 // #include "deparser.p4"
85
*/
sume_metadata.dst_port = 85;
}
action do_nothing() {
EthAddr_t temp = hdr.ethernet.dst_addr;
}
#ifdef ENABLE_CONTROLLER
#include "actions_controller.p4"
#endif
table lookup_table {
key = {
hdr.ethernet.dst_addr: exact;
}
actions = {
#ifdef ENABLE_CONTROLLER
controller_debug;
#endif
swap_eth_addresses;
do_nothing;
send_to_port1;
send_to_all_ports;
}
size = 64;
// default_action = swap_eth_addresses; // test_mirror(): in gen_testdata.py
default_action = send_to_port1; // test_port1()
// default_action = send_to_all_ports; // test_allports():
}
apply {
lookup_table.apply();
}
}
/********************************************************************************
* Deparser
*/
@Xilinx_MaxPacketRegion(1024)
control TopDeparser(packet_out packet,
in headers hdr,
//in user_metadata_t user_metadata,
in metadata meta,
inout digest_data_t digest_data,
inout sume_metadata_t sume_metadata) {
// @Xilinx_MaxPacketRegion(1024)
// control TopDeparser(packet_out b,
// in Parsed_packet p,
// inout digest_data_t digest_data,
// inout sume_metadata_t sume_metadata) {
apply {
packet.emit(hdr.ethernet);
}
// #include "deparser.p4"
}
/********************************************************************************
* Switch
*/
SimpleSumeSwitch(
TopParser(),
TopPipe(),
TopDeparser()
) main;