++ notes
This commit is contained in:
Nico Schottelius
parent
4059701f63
commit
880c228a76
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@ -13,6 +13,8 @@
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\vfil % or it might be \null
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\thispagestyle{plain}
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\begin{center}\textbf{Abstract}\end{center}
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In journal articles, research papers, published patent applications and patents, an abstract is a short summary placed prior to the introduction, often with different line justification (blockquote) from the rest of the article, used to help readers determine the purpose of the paper. While the length of the abstract varies by field of study, it is typically a paragraph in length (3-5 sentences), and never more than a page. See
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\url{en.wikipedia.org/wiki/Abstract(summary)} for details
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\vfil
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437
doc/plan.org
437
doc/plan.org
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@ -1415,7 +1415,7 @@ Please make sure that it is installed and available in your $PATH:
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** TODO Port to Hardware
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*** DONE Get access to tofino: no, NDA issues
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*** TODO Get NetFPGA running
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**** TODO Understand the simulations part
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**** DONE Understand the simulations part -> not atm
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**** DONE Install vivado
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**** DONE Install SDNET
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**** TODO Create either HDL or PX for supporting payload checksum
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@ -1790,7 +1790,7 @@ cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-swit
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cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/dma_0_log.axi': No such file or directory
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=== Running test /tmp/nico/test/simple_sume_switch/sim_switch_default ... using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py', '--sim', 'xsim']
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[15:31] rainbow:P4-NetFPGA%
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***** TODO run step 10: compiling the bitstream
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***** TODO run step 10: compiling the bitstream [takes hours]
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****** command
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#+BEGIN_CENTER
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cd $NF_DESIGN_DIR && make
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@ -1851,7 +1851,7 @@ Opening simple_sume_switch Implementation design
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado%
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#+END_CENTER
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****** TODO try3: debug the REAL failing command
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****** DONE try3: debug the REAL failing command
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******* command
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#+BEGIN_CENTER
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vivado -mode batch -source tcl/simple_sume_switch.tcl
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@ -1876,17 +1876,437 @@ ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
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"source ./tcl/control_sub.tcl"
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(file "tcl/simple_sume_switch.tcl" line 89)
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.... after bugfixing:
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Creating bitmap...
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Creating bitstream...
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Bitstream compression saved 132634496 bits.
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Writing bitstream ../bitfiles/simple_sume_switch.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Common 17-83] Releasing license: Implementation
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100 Infos, 51 Warnings, 1 Critical Warnings and 0 Errors encountered.
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write_bitstream completed successfully
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write_bitstream: Time (s): cpu = 00:02:39 ; elapsed = 00:03:20 . Memory (MB): peak = 4301.938 ; gain = 944.953 ; free physical
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= 23157 ; free virtual = 31451
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# exit
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INFO: [Common 17-206] Exiting Vivado at Mon May 20 13:07:53 2019...
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make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw'
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[13:07] rainbow:simple_sume_switch%
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#+END_CENTER
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******* TODO clarifying "simple_sume_switch.tcl"
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******** DONE What is it?
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Seems to be some kind of batch system for vivado
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******** DONE Who or what created it?
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Seems to be manually / from the project / not generated
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******** TODO Why is it incompatible?
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**** TODO Understand a bit of xilinx/netfpga/vivado
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******** DONE What is it trying to do?
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Assuming connecting "things" on the "board".
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******** DONE Why is it incompatible?
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******** DONE Trying to resolve the error 1: commenting out line 538
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# connect_bd_intf_net -intf_net nf_riffa_dma_1_pcie3_cfg_interrupt
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[get_bd_intf_pins nf_riffa_dma_1/cfg_interrupt] [get_bd_intf_pins
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pcie3_7x_1/pcie3_cfg_interrupt]
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****** DONE try4 going back to step 10 -> fails
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#+BEGIN_CENTER
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ume_switch/hw/project/simple_sume_switch.runs/control_sub_m00_data_fifo_0_synth_1/runme.log
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control_sub_s00_data_fifo_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_s00_data_fifo_0_synth_1/runme.log
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control_sub_auto_cc_0_synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/control_sub_auto_cc_0_synth_1/runme.log
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synth_1: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/synth_1/runme.log
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[Fri May 24 11:55:57 2019] Launched impl_1...
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Run output will be captured here: /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.runs/impl_1/runme.log
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launch_runs: Time (s): cpu = 00:00:34 ; elapsed = 00:01:10 . Memory (MB): peak = 2538.609 ; gain = 1199.879 ; free physical = 28377 ; free virtual = 34012
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# wait_on_run impl_1
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[Fri May 24 11:55:57 2019] Waiting for impl_1 to finish...
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[Fri May 24 12:39:07 2019] impl_1 finished
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wait_on_run: Time (s): cpu = 00:26:26 ; elapsed = 00:43:10 . Memory (MB): peak = 2538.609 ; gain = 0.000 ; free physical = 28208 ; free virtual = 34003
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# open_run impl_1
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ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
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Vivado% q
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#+END_CENTER
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****** DONE try5: error: No IP matching VLNV 'NetFPGA:NetFPGA:nf_sume_sdnet:*' was found
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#+BEGIN_CENTER
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[11:52] rainbow:hw% vivado -mode batch -source tcl/simple_sume_switch.tcl
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...
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### set NF_10G_INTERFACE3_BASEADDR $M07_BASEADDR
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### set NF_10G_INTERFACE3_HIGHADDR $M07_HIGHADDR
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### set NF_10G_INTERFACE3_SIZEADDR $M07_SIZEADDR
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### set NF_RIFFA_DMA_BASEADDR $M08_BASEADDR
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### set NF_RIFFA_DMA_HIGHADDR $M08_HIGHADDR
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### set NF_RIFFA_DMA_SIZEADDR $M08_SIZEADDR
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Wrote : </home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/project/simple_sume_switch.srcs/sources_1/bd/control_sub/control_sub.bd>
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# create_ip -name nf_sume_sdnet -vendor NetFPGA -library NetFPGA -module_name nf_sume_sdnet_ip
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ERROR: [Coretcl 2-1134] No IP matching VLNV 'NetFPGA:NetFPGA:nf_sume_sdnet:*' was found. Please check your repository configuration.
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INFO: [Common 17-206] Exiting Vivado at Sat May 25 11:52:01 2019...
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#+END_CENTER
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****** TODO try6: go back to clean netpfga-live, diff all sources
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#+BEGIN_CENTER
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[13:44] rainbow:~% diff -ru ~/P4-NetFPGA-live-clean/tools ~/projects/P4-NetFPGA/tools
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Only in /home/nico/projects/P4-NetFPGA/tools/scripts/NFTest: testcheck.pyc
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diff -ru /home/nico/P4-NetFPGA-live-clean/tools/settings.sh /home/nico/projects/P4-NetFPGA/tools/settings.sh
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--- /home/nico/P4-NetFPGA-live-clean/tools/settings.sh 2019-05-25 11:55:45.655636066 +0200
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+++ /home/nico/projects/P4-NetFPGA/tools/settings.sh 2019-05-13 11:49:02.122265641 +0200
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@@ -28,7 +28,8 @@
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# @NETFPGA_LICENSE_HEADER_END@
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#
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-export P4_PROJECT_NAME=switch_calc
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+export P4_PROJECT_NAME=switch_calc
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+export P4_PROJECT_NAME=minip4
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export NF_PROJECT_NAME=simple_sume_switch
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export SUME_FOLDER=${HOME}/projects/P4-NetFPGA
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export SUME_SDNET=${SUME_FOLDER}/contrib-projects/sume-sdnet-switch
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@@ -47,4 +48,3 @@
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export DRIVER_FOLDER=${SUME_FOLDER}/lib/sw/std/driver/${DRIVER_NAME}
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export APPS_FOLDER=${SUME_FOLDER}/lib/sw/std/apps/${DRIVER_NAME}
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export HWTESTLIB_FOLDER=${SUME_FOLDER}/lib/sw/std/hwtestlib
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-
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[13:44] rainbow:~%
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#+END_CENTER
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****** TODO try7: restart from beginning in minip4 alongside try6
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- steps 1...8 ok
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- step 9: fails to cp axi files
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- step 9: before that a python error
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****** DONE try8: fix python error in config_writes.py: script is generated
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#+BEGIN_CENTER
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# set_property compxlib.xsim_compiled_library_dir {} [current_project] [0/1819]
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# set_property top_lib xil_defaultlib [get_filesets sim_1]
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# update_compile_order -fileset sim_1
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update_compile_order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 2003.578 ; gain = 8.004 ; free physical = 27661 ; free virtual = 33990
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loading libsume..
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Traceback (most recent call last):
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/run.py", line 42, in <module>
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import config_writes
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File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
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^
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IndentationError: expected an indented block
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while executing
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"exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py"
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invoked from within
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"set output [exec python $::env(NF_DESIGN_DIR)/test/${test_name}/run.py]"
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(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/hw/tcl/simple_sume_switch_sim.tcl" line 177)
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INFO: [Common 17-206] Exiting Vivado at Sat May 25 13:45:13 2019...
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make: *** [Makefile:121: sim] Error 1
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make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test'
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512
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=== Work directory is /tmp/nico/test/simple_sume_switch
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=== Setting up test in /tmp/nico/test/simple_sume_switch/sim_switch_default
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#+END_CENTER
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config_writes.py
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#+BEGIN_CENTER
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[13:50] rainbow:~% find ~/P4-NetFPGA-live-clean -name config_writes.py
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[13:50] rainbow:~%
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#+END_CENTER
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******* File does not EXIST in original repo -> might be created in step6?
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"Generate the scripts that can be used in the NetFPGA SUME simulations to configure the table entries.
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$ cd $P4_PROJECT_DIR && make config_writes
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"
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#+BEGIN_CENTER!
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[13:50] rainbow:~% find ~/projects/P4-NetFPGA -name config_writes.py
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_writes.py
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py
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[13:53] rainbow:~%
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[13:53] rainbow:~% grep -r config_writes.py /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/vivado.log: File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/config_writes.py", line 7
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/Makefile: cp ${P4_PROJECT_DIR}/testdata/config_writes.py ./
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_default/Makefile: rm -f config_writes.py*
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/Makefile: cp ${P4_PROJECT_DIR}/testdata/config_writes.py ./
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/sim_switch_ctrlWrites/Makefile: rm -f config_writes.py*
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/Makefile: ${SUME_SDNET}/bin/gen_config_writes.py ${SDNET_OUT_DIR}/${P4_SWITCH}/config_writes.txt ${P4_SWITCH_BASE_ADDR} testdata
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[13:56] rainbow:~%
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#+END_CENTER
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Likely:
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/Makefile: ${SUME_SDNET}/bin/gen_config_writes.py ${SDNET_OUT_DIR}/${P4_SWITCH}/config_writes.txt ${P4_SWITCH_BASE_ADDR} testdata
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch
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[14:01] rainbow:sume-sdnet-switch% ls bin
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conv_p414_cmds gen_P4_SWITCH_externs.py libtcam_templates.pyc nf_sim_tools.pyc
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extern_data.py gen_P4_SWITCH_regs.py make_config_tables.py p4_px_tables.py
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extern_data.pyc libcam_templates.py make_new_p4_proj.py pcap2axi
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gen_config_fsm_writes.py libcam_templates.pyc make_regs_addressable.py sss_sume_metadata.py
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gen_config_writes.py liblpm_templates.py modify_P4_SWITCH_tb.py sss_sume_metadata.pyc
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gen_P4_SWITCH_API.py liblpm_templates.pyc nf_sim_compare_axi_logs.py
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gen_P4_SWITCH_CLI.py libtcam_templates.py nf_sim_tools.py
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[14:01] rainbow:sume-sdnet-switch%
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sim_config = 'config_writes.py'
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hw_config = 'config_writes.sh'
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****** DONE try9: debug the script that generates the script that generates the error
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#+BEGIN_CENTER
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[14:01] rainbow:sume-sdnet-switch% pwd
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch
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[14:01] rainbow:sume-sdnet-switch% ls bin
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conv_p414_cmds gen_P4_SWITCH_externs.py libtcam_templates.pyc nf_sim_tools.pyc
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extern_data.py gen_P4_SWITCH_regs.py make_config_tables.py p4_px_tables.py
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extern_data.pyc libcam_templates.py make_new_p4_proj.py pcap2axi
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gen_config_fsm_writes.py libcam_templates.pyc make_regs_addressable.py sss_sume_metadata.py
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gen_config_writes.py liblpm_templates.py modify_P4_SWITCH_tb.py sss_sume_metadata.pyc
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gen_P4_SWITCH_API.py liblpm_templates.pyc nf_sim_compare_axi_logs.py
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gen_P4_SWITCH_CLI.py libtcam_templates.py nf_sim_tools.py
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#+END_CENTER
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Find the input file to find the script call directory
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#+BEGIN_CENTER
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[14:04] rainbow:sume-sdnet-switch% find ~/projects/P4-NetFPGA -name config_writes.txt
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/home/nico/projects/P4-NetFPGA/lib/hw/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt
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[14:08] rainbow:sume-sdnet-switch%
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#+END_CENTER
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Input data in nf_sume_sdnet_ip is:
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#+BEGIN_CENTER
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<addr, data>: (00000020, 00000001)
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<addr, data>: (00000020, 00000000)
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#+END_CENTER
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Original call in the Makefile:
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#+BEGIN_CENTER
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[14:10] rainbow:minip4% make config_writes
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
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[14:10] rainbow:minip4%
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#+END_CENTER
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Understading gen_config_writes.py:
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#+BEGIN_CENTER
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('filename', type=str, help="the config_writes.txt file")
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parser.add_argument('baseaddr', type=str, help="the base address of the P4_SWITCH")
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parser.add_argument('outdir', type=str, help="the name of the output directory")
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args = parser.parse_args()
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dic = parse_config_writes(args.filename)
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new_dic = remove_init_addresses(dic)
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write_sim_config(new_dic, int(args.baseaddr, 0), args.outdir)
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write_hw_config(new_dic, int(args.baseaddr, 0), args.outdir)
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#+END_CENTER
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read arguments, create a dictionary by removing init addresses (why?
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which?), create the two output files, one of them being
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config_writes.py that does not have any lines.
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#+BEGIN_CENTER
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def parse_config_writes(filename):
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regex = r"<addr, data>: \(([abcdefABCDEF\d]*), ([abcdefABCDEF\d]*)\)"
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dic = collections.OrderedDict()
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i = 0
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with open(filename) as f:
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for line in f:
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searchObj = re.match(regex, line)
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if searchObj is not None:
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dic[i] = (searchObj.group(1), searchObj.group(2))
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else:
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print >> sys.stderr, "ERROR: encountered unexpected line in file: \n", line
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sys.exit(1)
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i += 1
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return dic
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#+END_CENTER
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Looks for all matching lines, errors out if wrong lines are in there.
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#+BEGIN_CENTER
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def remove_init_addresses(dic):
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result = collections.OrderedDict()
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for (index, tup) in dic.iteritems():
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if tup[0][-2:] != "20":
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result[index] = tup
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return result
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#+END_CENTER
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|
||||
Adding debug:
|
||||
|
||||
#+BEGIN_CENTER
|
||||
def main():
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument('filename', type=str, help="the config_writes.txt file")
|
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parser.add_argument('baseaddr', type=str, help="the base address of the P4_SWITCH")
|
||||
parser.add_argument('outdir', type=str, help="the name of the output directory")
|
||||
args = parser.parse_args()
|
||||
|
||||
dic = parse_config_writes(args.filename)
|
||||
print("orig dic: {}".format(dic))
|
||||
new_dic = remove_init_addresses(dic)
|
||||
print("new dic: {}".format(new_dic))
|
||||
write_sim_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||
write_hw_config(new_dic, int(args.baseaddr, 0), args.outdir)
|
||||
|
||||
#+END_CENTER
|
||||
|
||||
Output:
|
||||
|
||||
#+BEGIN_CENTER
|
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nfig_writes.txt 0x44020000 testdata
|
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[14:10] rainbow:minip4% make config_writes
|
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/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/gen_config_writes.py nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt 0x44020000 testdata
|
||||
orig dic: OrderedDict([(0, ('00000020', '00000001')), (1, ('00000020', '00000000'))])
|
||||
new dic: OrderedDict()
|
||||
[14:15] rainbow:minip4%
|
||||
|
||||
#+END_CENTER
|
||||
|
||||
-> Problem seems to be that no addresses are left. Why?
|
||||
|
||||
|
||||
****** TODO try10: find out, why nf_sume_sdnet_ip/SimpleSumeSwitch/config_writes.txt has too less content
|
||||
|
||||
***** run step 11: checking design -- skipped
|
||||
***** TODO run step 12: ok
|
||||
****** code
|
||||
#+BEGIN_CENTER
|
||||
cd $NF_DESIGN_DIR/bitfiles && \
|
||||
mv simple_sume_switch.bit ${P4_PROJECT_NAME}.bit && \
|
||||
cp $P4_PROJECT_DIR/testdata/config_writes.sh ./
|
||||
#+END_CENTER
|
||||
***** TODO run step 13:
|
||||
****** command
|
||||
#+BEGIN_CENTER
|
||||
cd $NF_DESIGN_DIR/bitfiles/ && sudo bash ./program_switch.sh
|
||||
#+END_CENTER
|
||||
****** DONE try1: paths not setup for root
|
||||
[14:54] rainbow:bitfiles% cd $NF_DESIGN_DIR/bitfiles/ && sudo bash ./program_switch.sh
|
||||
./program_switch.sh: line 34: /tools/program_switch.sh: No such file or directory
|
||||
[14:56] rainbow:bitfiles% ls
|
||||
config_writes.sh minip4.bit program_switch.sh README
|
||||
[14:56] rainbow:bitfiles%
|
||||
****** DONE try2: setup paths as root: various other errors
|
||||
#+BEGIN_CENTER
|
||||
root@rainbow:~# cd $NF_DESIGN_DIR/bitfiles/ && bash ./program_switch.sh
|
||||
rmmod: ERROR: Module sume_riffa is not currently loaded
|
||||
rlwrap: warning: your $TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
|
||||
RUN loading image file.
|
||||
switch_calc.bit
|
||||
attempting to launch hw_server
|
||||
****** Xilinx hw_server v2018.2
|
||||
**** Build date : Jun 14 2018-20:18:37
|
||||
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
INFO: hw_server application started
|
||||
INFO: Use Ctrl-C to exit hw_server application
|
||||
|
||||
INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121
|
||||
|
||||
|
||||
couldn't open "switch_calc.bit": no such file or directory
|
||||
invoked from within
|
||||
"::tcf::eval -progress ::xsdb::print_progress {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {process_tcf_actions_cache_client ::tcfclient#0::arg}}}"
|
||||
(procedure "::tcf::cache_eval_with_progress" line 2)
|
||||
invoked from within
|
||||
"::tcf::cache_eval_with_progress [dict get $arg chan] [list process_tcf_actions_cache_client $argvar] $progress"
|
||||
(procedure "process_tcf_actions" line 1)
|
||||
invoked from within
|
||||
"process_tcf_actions $arg ::xsdb::print_progress"
|
||||
(procedure "fpga" line 430)
|
||||
invoked from within
|
||||
"fpga -f $bitimage"
|
||||
(file "/root/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_xsct.tcl" line 33)
|
||||
Check programming FPGA or Reboot machine !
|
||||
rmmod: ERROR: Module sume_riffa is not currently loaded
|
||||
nf0: ERROR while getting interface flags: No such device
|
||||
nf1: ERROR while getting interface flags: No such device
|
||||
nf2: ERROR while getting interface flags: No such device
|
||||
nf3: ERROR while getting interface flags: No such device
|
||||
|
||||
#+END_CENTER
|
||||
****** TODO try3: adjusting/analysing "./program_switch.sh"
|
||||
Calls another script
|
||||
#+BEGIN_CENTER
|
||||
|
||||
# Program the switch with the bit file and then configure the tables
|
||||
${SUME_SDNET}/tools/program_switch.sh switch_calc.bit config_writes.sh
|
||||
#+END_CENTER
|
||||
****** TODO try4: analyse ANOTHER program_switch.sh
|
||||
#+BEGIN_CENTER
|
||||
root@rainbow:~/projects/P4-NetFPGA# find . -name program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/projects/int/simple_sume_switch/bitfiles/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/projects/minip4/simple_sume_switch/bitfiles/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/projects/switch_calc/simple_sume_switch/bitfiles/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/projects/learning_switch/simple_sume_switch/bitfiles/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/projects/tcp_monitor/simple_sume_switch/bitfiles/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/tools/program_switch.sh
|
||||
./contrib-projects/sume-sdnet-switch/templates/sss_p4_proj/simple_sume_switch/bitfiles/program_switch.sh
|
||||
root@rainbow:~/projects/P4-NetFPGA#
|
||||
|
||||
#+END_CENTER
|
||||
|
||||
Add set -x debugging, see real error
|
||||
|
||||
#+BEGIN_CENTER
|
||||
|
||||
#+END_CENTER
|
||||
****** TODO try 5: reboot && retry
|
||||
#+BEGIN_CENTER
|
||||
[9:24] rainbow:~% sudo -i
|
||||
root@rainbow:~# lsmod | grep riffa
|
||||
root@rainbow:~# modprobe sume_riffa
|
||||
modprobe: FATAL: Module sume_riffa not found in directory /lib/modules/5.0.0-15-generic
|
||||
root@rainbow:~#
|
||||
#+END_CENTER
|
||||
-> not changing
|
||||
|
||||
|
||||
|
||||
******* DONE Going back to setup steps
|
||||
[10:11] rainbow:tcam_v1_1_0% cd $SUME_FOLDER/lib/hw/xilinx/cores/tcam_v1_1_0/ && make update && make
|
||||
cd $SUME_FOLDER/lib/hw/xilinx/cores/cam_v1_1_0/ && make update && make
|
||||
cd $SUME_SDNET/sw/sume && make
|
||||
cd $SUME_FOLDER && make
|
||||
|
||||
-> all good so far
|
||||
|
||||
cd $DRIVER_FOLDER
|
||||
make all
|
||||
sudo make install
|
||||
sudo modprobe sume_riffa
|
||||
|
||||
|
||||
|
||||
#+BEGIN_CENTER
|
||||
[11:44] rainbow:sume_riffa_v1_0_0% sudo make install
|
||||
make -C /lib/modules/5.0.0-15-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_riffa_v1_0_0 modules
|
||||
make[1]: Entering directory '/usr/src/linux-headers-5.0.0-15-generic'
|
||||
Building modules, stage 2.
|
||||
MODPOST 1 modules
|
||||
make[1]: Leaving directory '/usr/src/linux-headers-5.0.0-15-generic'
|
||||
install -o root -g root -m 0755 -d /lib/modules/5.0.0-15-generic/extra/sume_riffa/
|
||||
install -o root -g root -m 0755 sume_riffa.ko /lib/modules/5.0.0-15-generic/extra/sume_riffa/
|
||||
depmod -a 5.0.0-15-generic
|
||||
[11:44] rainbow:sume_riffa_v1_0_0%
|
||||
|
||||
[11:44] rainbow:sume_riffa_v1_0_0% lsmod | grep sume_riffa
|
||||
sume_riffa 28672 0
|
||||
[11:45] rainbow:sume_riffa_v1_0_0%
|
||||
|
||||
#+END_CENTER
|
||||
|
||||
|
||||
**** DONE Understand a bit of xilinx/netfpga/vivado ~ somewhat
|
||||
- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf
|
||||
|
||||
|
||||
The xvhdl and xvlog commands parse VHDL and Verilog files, respectively. Descriptions
|
||||
for each option are available in Table 5-2, page 102.
|
||||
|
||||
|
|
@ -1908,7 +2328,6 @@ command along with other options to effect HDL simulation
|
|||
VHDL->[via xvhdl]-> HDL
|
||||
Verilog->[via xvlog]->HDL
|
||||
|
||||
|
||||
***** TODO Understand SimpleSumeSwitch
|
||||
SimpleSumeSwitch(
|
||||
TopParser(),
|
||||
|
|
@ -2405,6 +2824,8 @@ what.
|
|||
was generated by a step that is not clear what it is supposed to do
|
||||
- one step huge output, hundreds to thousands of lines, errors
|
||||
somewher in between => exceeding tmux buffers
|
||||
- some steps take VERY long correctly
|
||||
- some steps stopped in an infinite loop => hard to distinguish
|
||||
- non fatal/fatal errors cannot be distinguished
|
||||
grep: ../../../RELEASE_NOTES: No such file or directory
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue