\chapter { \label { appendixminus1} Resources and code repositories}
The following sections describe how to acquire the resources
to reproduce the test results.
% ----------------------------------------------------------------------
\section { \label { chapterminus1:thesis:os} Operating Systems}
All P4 compilations were made on Ubuntu 16.04 with kernels
\begin { itemize}
\item 4.15.0-54-generic (Supporting Desktop)
\item 4.4.0-143-generic (BMV2 test VM)
\item 4.15.0-55-generic (Desktop with NetFPGA card)
\end { itemize}
% ok
% ----------------------------------------------------------------------
\section { \label { chapterminus1:thesis:general} Master Thesis}
The master thesis including all self developed source code is
available by git via
\begin { itemize}
\item git clone \url { git@gitlab.ethz.ch:nicosc/master-thesis.git}
\item git clone \url { git@gitlab.ethz.ch:nsg/student-projects/ma-2019-19_ high_ speed_ nat64_ with_ p4}
\end { itemize}
It can be browsed online on
\url { https://gitlab.ethz.ch/nicosc/master-thesis} and on
\url { https://gitlab.ethz.ch/nsg/student-projects/ma-2019-19_ high_ speed_ nat64_ with_ p4} .
% ok
% ----------------------------------------------------------------------
\section { \label { chapterminus1:thesis:xilinx} Xilinx Toolchain}
A prerequisite for building the NetFGPA source code is the
installation of
\begin { itemize}
\item \texttt { Xilinx\_ SDNet\_ 2018.2\_ 1005\_ 9}
\item \texttt { Xilinx\_ Vivado\_ SDK\_ 2018\. 2\_ 0614\_ 1954}
\end { itemize}
Both tools need to be installed to \texttt { /opt/Xilinx/} ,
as paths are hardcoded in various places.
% ok
% ----------------------------------------------------------------------
\section { \label { chapterminus1:thesis} P4/NetFGPA Support Scripts}
To be able to compile P4 source code to the NetFPGA the collection of
scripts, Makefiles and sample code of P4-NetFGPA is required.
The repository \url { git@github.com:NetFPGA/P4-NetFPGA-live.git} needs
to be cloned to ``projects'' subdirectory as ``P4-NetPFGA''
of the user that wants to
compile the source code. Access to the repository is granted after
applying for access as described on
\url { https://github.com/NetFPGA/P4-NetFPGA-public/wiki} .
After that the variable \texttt { P4\_ PROJECT\_ NAME} in
\texttt { ~/projects/P4-NetFPGA/tools/settings.sh} needs to be modified to
read \texttt { export P4\_ PROJECT\_ NAME=minip4}
instead of \texttt { export P4\_ PROJECT\_ NAME=switch\_ calc} .
Sample code for installation:
\begin { tiny} \begin { verbatim}
mkdir -p ~/projects
git clone git@github.com:NetFPGA/P4-NetFPGA-live.git P4-NetFPGA
sed -i 's/\( P 4 _ PROJECT _ NAME = \) .*/\1 minip4/' ~/projects/P4-NetFPGA/tools/settings.sh
\end { verbatim}
\end { tiny}
Version \textbf { v1.3.1-46-g97d3aaa} of the P4-NetPFGA repository was
used for creating the bitfiles of this project.
\begin { verbatim}
nico@nsg-System:~/projects/P4-NetFPGA$ git describe - - always
v1.3.1-46-g97d3aaa
\end { verbatim}
% ok
% ----------------------------------------------------------------------
\section { \label { appendix:netfpga:compile} P4/NetFGPA Compilation Process}
After having setup the compile host as described above, the script
\texttt { bin/do-all-steps.sh} that is included in the thesis' git
repository. With a NetFPGA card installed in the host, this script
will compile the P4 source code to PX and in a second step to HDL and
then upload the resulting bitstream to the NetFPGA. The compilation
process will log its output to the directory
\texttt { \~ /master-thesis/netpfga/log/} .
% ----------------------------------------------------------------------
\section { \label { appendix:netfpga:tests} P4/NetFGPA Tests}
In the following sections we describe functionality tests
of our code on the NetFPGA.
% ----------------------------------------------------------------------
\subsection { Test 1: IPv4 Egress}
In this test we test whether setting the output port based on the
IPv4 address.
First we get the integer values of the IPv4 addresses in python:
\begin { verbatim}
>>> int(ipaddress.IPv4Address(u"10.0.0.42"))
167772202
>>> int(ipaddress.IPv4Address(u"10.0.0.4"))
167772164
>>>
\end { verbatim}
After that we set the table table entries for the NetFPGA.
\begin { tiny} \begin { verbatim}
>> table_ cam_ add_ entry realmain_ v4_ networks_ 0 realmain.set_ egress_ port 167772202 => 16 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
action_ name = TopPipe.realmain.set_ egress_ port
field_ vals = [1, '16', '0', '0', '0', '0']
CAM_ Init_ ValidateContext() - done
WROTE 0x44020250 = 0xa00002a
WROTE 0x44020280 = 0x0000
WROTE 0x44020284 = 0x0000
WROTE 0x44020288 = 0x10000000
WROTE 0x4402028c = 0x0001
READ 0x44020244 = 0x0001
WROTE 0x44020240 = 0x0001
READ 0x44020244 = 0x0001
READ 0x44020244 = 0x0001
success
>> table_ cam_ add_ entry realmain_ v4_ networks_ 0 realmain.set_ egress_ port 167772164 => 16 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
action_ name = TopPipe.realmain.set_ egress_ port
field_ vals = [1, '16', '0', '0', '0', '0']
CAM_ Init_ ValidateContext() - done
WROTE 0x44020250 = 0xa000004
WROTE 0x44020280 = 0x0000
WROTE 0x44020284 = 0x0000
WROTE 0x44020288 = 0x10000000
WROTE 0x4402028c = 0x0001
READ 0x44020244 = 0x0001
WROTE 0x44020240 = 0x0001
READ 0x44020244 = 0x0001
READ 0x44020244 = 0x0001
success
>>
\end { verbatim}
\end { tiny}
On the host we setup the ARP entries:
\begin { tiny} \begin { verbatim}
root@ESPRIMO-P956:~# ip neigh add 10.0.0.6 lladdr f8:f2:1e:09:62:d1 dev enp2s0f0
root@ESPRIMO-P956:~# ip neigh add 10.0.0.4 lladdr f8:f2:1e:09:62:d1 dev enp2s0f0
\end { verbatim}
\end { tiny}
And then we generate test packets and expect 4 packets to show up on
enp2s0f0.
The following \texttt { tcpdump} output shows the expected packets
arriving on enp2s0f0:
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ sudo tcpdump - ni enp 2 s 0 f 0
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on enp2s0f0, link-type EN10MB (Ethernet), capture size 262144 bytes
10:49:28.200407 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 1, length 64
10:49:28.200445 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 1, length 64
10:49:29.222340 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 2, length 64
10:49:29.222418 IP 10.0.0.42 > 10.0.0.4: ICMP echo request, id 4440, seq 2, length 64
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\subsection { Test 2: IPv6 Egress}
This test shows how setting the egress port based on the IPv6 address
works with the NetPFGA. Similar to the previous test, we first the
the Integer values of the IPv6 addresses:
\begin { verbatim}
>>> int(ipaddress.IPv6Address(u"2001:db8:42::4"))
42540766411362381960998550477184434180L
>>> int(ipaddress.IPv6Address(u"2001:db8:42::6"))
42540766411362381960998550477184434182L
>>> int(ipaddress.IPv6Address(u"2001:db8:42::42"))
42540766411362381960998550477184434242L
\end { verbatim}
After that we set the table entries:
\begin { tiny}
\begin { verbatim}
>> table_ cam_ add_ entry realmain_ v6_ networks_ 0 realmain.set_ egress_ port 42540766411362381960998550477184434182 => 64 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
action_ name = TopPipe.realmain.set_ egress_ port
field_ vals = [1, '64', '0', '0', '0', '0']
CAM_ Init_ ValidateContext() - done
WROTE 0x44020350 = 0x0006
WROTE 0x44020354 = 0x0000
WROTE 0x44020358 = 0x420000
WROTE 0x4402035c = 0x20010db8
WROTE 0x44020380 = 0x0000
WROTE 0x44020384 = 0x0000
WROTE 0x44020388 = 0x40000000
WROTE 0x4402038c = 0x0001
READ 0x44020344 = 0x0001
WROTE 0x44020340 = 0x0001
READ 0x44020344 = 0x0001
READ 0x44020344 = 0x0001
success
>> table_ cam_ add_ entry realmain_ v6_ networks_ 0 realmain.set_ egress_ port 42540766411362381960998550477184434242 => 64 0 0 0 0
fields = [(u'hit', 1), (u'action_ run', 3), (u'out_ port', 8), (u'out_ port', 8), (u'mac_ addr', 48), (u'task', 16), (u'table_ id', 16)]
action_ name = TopPipe.realmain.set_ egress_ port
field_ vals = [1, '64', '0', '0', '0', '0']
CAM_ Init_ ValidateContext() - done
WROTE 0x44020350 = 0x0042
WROTE 0x44020354 = 0x0000
WROTE 0x44020358 = 0x420000
WROTE 0x4402035c = 0x20010db8
WROTE 0x44020380 = 0x0000
WROTE 0x44020384 = 0x0000
WROTE 0x44020388 = 0x40000000
WROTE 0x4402038c = 0x0001
READ 0x44020344 = 0x0001
WROTE 0x44020340 = 0x0001
READ 0x44020344 = 0x0001
READ 0x44020344 = 0x0001
success
>>
\end { verbatim}
\end { tiny}
On the host we set the IPv6 neighbor entries:
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ sudo ip - 6 neigh add 2001 :db 8 : 42 :: 6 lladdr f 8 :f 2 : 1 e: 09 : 62 :d 0 dev enp 2 s 0 f 1
nico@ESPRIMO-P956:~$ sudo ip - 6 neigh add 2001 :db 8 : 42 :: 4 lladdr f 8 :f 2 : 1 e: 09 : 62 :d 0 dev enp 2 s 0 f 1
\end { verbatim}
\end { tiny}
And generate the test packets:
\begin { tiny} \begin { verbatim}
nico@ESPRIMO-P956:~$ ping 6 - c 2 2001 :db 8 : 42 :: 6
PING 2001:db8:42::6(2001:db8:42::6) 56 data bytes
nico@ESPRIMO-P956:~$ sudo tcpdump - ni enp 2 s 0 f 1
tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
listening on enp2s0f1, link-type EN10MB (Ethernet), capture size 262144 bytes
11:30:17.287577 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 1, length 64
11:30:17.287599 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 1, length 64
11:30:18.310178 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 2, length 64
11:30:18.310258 IP6 2001:db8:42::42 > 2001:db8:42::6: ICMP6, echo request, seq 2, length 64
\end { verbatim}
\end { tiny}
The packets are successfully seen by tcpdump.
% ----------------------------------------------------------------------
\section { \label { appendix:bmv2} P4/BMV2 Environment and Tests}
All BMV2 based compilations were made with the following compiler:
\begin { verbatim}
p4@ubuntu:~$ p 4 c - - version
p4c 0.5 (SHA: 5ae30ee)
\end { verbatim}
The installation is based on the vagrant files that were provided in
the ``Advanced Topics in
Communication Networks Fall 2018'' course of
ETHZ (\url { https://adv-net.ethz.ch/2018/} ) and contains p4tools as
well as all utilities that came with the vagrant installation.
% ok
% ----------------------------------------------------------------------
For running the diff based checksum code, the following steps are
necessary: First compile the p4 code and then start the switch, both
with \texttt { p4run} .
\begin { verbatim}
cd ~/master-thesis/p4app
sudo p4run --config nat64-diff.json
\end { verbatim}
Then with starting the controller the required table entries will
\begin { verbatim}
cd ~/master-thesis/p4app
sudo python ./controller.py --mode range_ router
\end { verbatim}
% ----------------------------------------------------------------------
\chapter { \label { appendix:netpfgalogs} NetFPGA Logs}
The log files of the NetFPGA compilations are stored inside
the source code directory stored at \texttt { netpfga/logs} .
It follows a selection of excerpts of log files that might
be relevant for reproducing the work.
% ----------------------------------------------------------------------
\section { \label { appendix:netpfgalogs:flasherror} NetFPGA Flash Errors}
Sometimes flashing bitfiles to the NetFPGA will fail. A random amount
of reboots (1 to 3) and a random amount of reflashing will fix this
problem.
Below can be found the log output from the flashing process.
\begin { tiny} \begin { verbatim}
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
sudo bash -c ". $ HOME / master - thesis / netpfga / bashinit & & $ (pwd -P)/program_ switch.sh"
++ which vivado
+ xilinx_ tool_ path=/opt/Xilinx/Vivado/2018.2/bin/vivado
+ bitimage=minip4.bit
+ configWrites=config_ writes.sh
+ '[' -z minip4.bit ']'
+ '[' -z config_ writes.sh ']'
+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
+ rmmod sume_ riffa
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_ xsct.tcl -tclargs minip4.bit
rlwrap: warning: your $ TERM is 'screen' but rlwrap couldn't find it in the terminfo database. Expect some problems.
RUN loading image file.
minip4.bit
100% 19MB 1.7MB/s 00:11
fpga configuration failed. DONE PIN is not HIGH
invoked from within
"::tcf::eval -progress ::xsdb::print_ progress { ::tcf::cache_ enter tcfchan#0 { tcf_ cache_ eval { process_ tcf_ actions_ cache_ client ::tcfclient#0::arg} } } "
(procedure "::tcf::cache_ eval_ with_ progress" line 2)
invoked from within
"::tcf::cache_ eval_ with_ progress [dict get $ arg chan ] [ list process _ tcf _ actions _ cache _ client $ argvar] $ progress"
(procedure "process_ tcf_ actions" line 1)
invoked from within
"process_ tcf_ actions $ arg ::xsdb::print _ progress"
(procedure "fpga" line 430)
invoked from within
"fpga -f $ bitimage"
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_ xsct.tcl" line 33)
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_ rescan_ run.sh
Check programming FPGA or Reboot machine !
+ rmmod sume_ riffa
rmmod: ERROR: Module sume_ riffa is not currently loaded
+ modprobe sume_ riffa
+ ifconfig nf0 up
nf0: ERROR while getting interface flags: No such device
+ ifconfig nf1 up
nf1: ERROR while getting interface flags: No such device
+ ifconfig nf2 up
nf2: ERROR while getting interface flags: No such device
+ ifconfig nf3 up
nf3: ERROR while getting interface flags: No such device
+ bash config_ writes.sh
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\section { \label { appendix:netpfgalogs:flashsuccess} NetFPGA Flash Success}
A successful flashing process also emits a couple of errors, however
the message ``fpga configuration failed. DONE PIN is not HIGH'' and
its succeeding lines are missing, as seen below.
After that in all cases a reboot is required; the PCI rescan in none
of our test cases re enabled the nf devices.
\begin { tiny} \begin { verbatim}
nico@nsg-System:~$ cd $ NF_ DESIGN_ DIR/bitfiles/
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
sudo bash -c ". $ HOME / master - thesis / netpfga / bashinit & & $ (pwd -P)/program_ switch.sh"
++ which vivado
+ xilinx_ tool_ path=/opt/Xilinx/Vivado/2018.2/bin/vivado
+ bitimage=minip4.bit
+ configWrites=config_ writes.sh
+ '[' -z minip4.bit ']'
+ '[' -z config_ writes.sh ']'
+ '[' /opt/Xilinx/Vivado/2018.2/bin/vivado == '' ']'
+ rmmod sume_ riffa
+ xsct /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/run_ xsct.tcl -tclargs minip4.bit
rlwrap: warning: your $ TERM is 'xterm - 256 color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
RUN loading image file.
minip4.bit
attempting to launch hw_ server
****** Xilinx hw_ server v2018.2
**** Build date : Jun 14 2018-20:18:37
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
INFO: hw_ server application started
INFO: Use Ctrl-C to exit hw_ server application
INFO: To connect to this hw_ server instance use url: TCP:127.0.0.1:3121
100% 19MB 1.7MB/s 00:11
+ bash /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/tools/pci_ rescan_ run.sh
Check programming FPGA or Reboot machine !
+ rmmod sume_ riffa
rmmod: ERROR: Module sume_ riffa is not currently loaded
+ modprobe sume_ riffa
+ ifconfig nf0 up
nf0: ERROR while getting interface flags: No such device
+ ifconfig nf1 up
nf1: ERROR while getting interface flags: No such device
+ ifconfig nf2 up
nf2: ERROR while getting interface flags: No such device
+ ifconfig nf3 up
nf3: ERROR while getting interface flags: No such device
+ bash config_ writes.sh
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/bitfiles$
\end { verbatim}
\end { tiny}
% ok
% ----------------------------------------------------------------------
\section { \label { appendix:netfpgalogs:kernelmodule} NetFPGA Kernel Module}
After a successful flash, loading the kernel module will enable nf
devices to appear in the operating system.
\begin { tiny} \begin { verbatim}
nico@nsg-System:~$ ip l
1: lo: <LOOPBACK,UP,LOWER_ UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_ UP> mtu 1500 qdisc pfifo_ fast state UP mode DEFAULT group default qlen 1000
link/ether 74:d0:2b:98:38:f6 brd ff:ff:ff:ff:ff:ff
3: eth1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9c brd ff:ff:ff:ff:ff:ff
4: eth2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9d brd ff:ff:ff:ff:ff:ff
5: wg0: <POINTOPOINT,NOARP,UP,LOWER_ UP> mtu 1420 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/none
nico@nsg-System:~$ ~ / master - thesis / bin / build - load - drivers.sh
+ cd /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0
+ sudo modprobe -r sume_ riffa
+ make clean
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0 clean
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0/.tmp_ versions
CLEAN /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0/Module.symvers
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ make all
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
CC [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0/sume_ riffa.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0/sume_ riffa.mod.o
LD [M] /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0/sume_ riffa.ko
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
+ sudo make install
make -C /lib/modules/4.15.0-55-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0 modules
make[1]: Entering directory '/usr/src/linux-headers-4.15.0-55-generic'
Building modules, stage 2.
MODPOST 1 modules
make[1]: Leaving directory '/usr/src/linux-headers-4.15.0-55-generic'
install -o root -g root -m 0755 -d /lib/modules/4.15.0-55-generic/extra/sume_ riffa/
install -o root -g root -m 0755 sume_ riffa.ko /lib/modules/4.15.0-55-generic/extra/sume_ riffa/
depmod -a 4.15.0-55-generic
+ sudo modprobe sume_ riffa
+ grep sume_ riffa
+ lsmod
sume_ riffa 28672 0
nico@nsg-System:~$
nico@nsg-System:~$ ip l
1: lo: <LOOPBACK,UP,LOWER_ UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_ UP> mtu 1500 qdisc pfifo_ fast state UP mode DEFAULT group default qlen 1000
link/ether 74:d0:2b:98:38:f6 brd ff:ff:ff:ff:ff:ff
3: eth1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9c brd ff:ff:ff:ff:ff:ff
4: eth2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether f8:f2:1e:41:44:9d brd ff:ff:ff:ff:ff:ff
5: wg0: <POINTOPOINT,NOARP,UP,LOWER_ UP> mtu 1420 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/none
6: nf0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:00 brd ff:ff:ff:ff:ff:ff
7: nf1: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:01 brd ff:ff:ff:ff:ff:ff
8: nf2: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:02 brd ff:ff:ff:ff:ff:ff
9: nf3: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
link/ether 02:53:55:4d:45:03 brd ff:ff:ff:ff:ff:ff
nico@nsg-System:~$
\end { verbatim}
\end { tiny}
% ----------------------------------------------------------------------
\section { \label { appendix:netfpgalogs:compilelogs} NetFPGA Compile Logs}
% ----------------------------------------------------------------------
This section shows a compilation of of NetFPGA compile output and errors.
Unfound tbl files that are not correctly generated fail the compilation:
\begin { tiny} \begin { verbatim}
# Fix introduced for SDNet 2017.4
sed -i 's/xsim\. dir\/ xsc\/ dpi\. so/dpi\. so/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim.bash
sed -i 's/xsim\. dir\/ xsc\/ dpi\. so/dpi\. so/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_ sim/glbl/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
sed -i 's/SimpleSumeSwitch_ tb_ sim#work.glbl/SimpleSumeSwitch_ tb/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
cp src/*.tbl nf_ sume_ sdnet_ ip/SimpleSumeSwitch/
cp: cannot stat 'src/*.tbl': No such file or directory
make: *** [Makefile:23: cpp_ test] Error 1
[23:12] loch:minip4%
\end { verbatim}
\end { tiny}
Failure to generate an intermediate file:
\begin { tiny} \begin { verbatim}
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/obj/xsim_ 3.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
\end { verbatim}
\end { tiny}
Failure to compile because libncurses.so.5 is missing:
\begin { tiny} \begin { verbatim}
/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang -fPIC -c -std=gnu89 -nobuiltininc -nostdinc++ -w -Wl,--unres
olved-symbols=ignore-in-object-files -fbracket-depth=1048576 -I/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/../li
b/clang/3.1/include -fPIC -m64 -I"/opt/Xilinx/Vivado/2018.2/data/xsim/include" "xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/ob
j/xsim_ 3.c" -O0 -sim -o "xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/obj/xsim_ 3.lnx64.o" -DXILINX_ SIMULATOR
/opt/Xilinx/Vivado/2018.2/data/../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot
open shared object file: No such file or directory
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.SimpleSumeSwitch_ tb#work.glbl/obj/xsim_ 3.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
[20:00] rainbow:SimpleSumeSwitch%
\end { verbatim}
\end { tiny}
Failure to access txt files that were not correctly generated in a
different compilation step:
\begin { tiny} \begin { verbatim}
# Fix introduced for SDNet 2018.2
sed -i 's/glbl_ sim/glbl/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
sed -i 's/SimpleSumeSwitch_ tb_ sim#work.glbl/SimpleSumeSwitch_ tb/g' nf_ sume_ sdnet_ ip/SimpleSumeSwitch/vivado_ sim_ waveform.bash
cp src/*.tbl nf_ sume_ sdnet_ ip/SimpleSumeSwitch/
cp testdata/*.txt nf_ sume_ sdnet_ ip/SimpleSumeSwitch/
cp: cannot stat 'testdata/*.txt': No such file or directory
make: *** [Makefile:17: all] Error 1
[15:46] rainbow:minip4%
\end { verbatim}
\end { tiny}
Missing pcap files of non generated testdata causing compile abortion:
\begin { tiny} \begin { verbatim}
make -C testdata/
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
./gen_ testdata.py
/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi --output Packet_ in.axi --bus_ width 256 src.pcap
Traceback (most recent call last):
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 108, in <module>
write_ to_ file(args.file_ pcap, args.output)
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/bin/pcap2axi", line 88, in write_ to_ file
for pkt in rdpcap(file_ in):
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 728, in rdpcap
with PcapReader(filename) as fdesc:
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 751, in _ _ call_ _
filename, fdesc, magic = cls.open(filename)
File "/usr/lib/python2.7/dist-packages/scapy/utils.py", line 778, in open
fdesc = open(filename, "rb")
IOError: [Errno 2] No such file or directory: 'src.pcap'
make[1]: *** [Makefile:5: all] Error 1
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata'
make: *** [Makefile:32: frontend] Error 2
[15:47] rainbow:minip4%
\end { verbatim}
\end { tiny}
Syntax errors due to incorrect generation of a python script:
\begin { tiny}
\begin { verbatim}
update_ compile_ order: Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 1995.594 ; gain = 0.016 ; free physic
al = 21975 ; free virtual = 33161
loading libsume..
Traceback (most recent call last):
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ de
fault/run.py", line 42, in <module>
import config_ writes
File "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ de
fault/config_ writes.py", line 7
^
IndentationError: expected an indented block
while executing
"exec python $ ::env ( NF _ DESIGN _ DIR ) / test / $ { test_ name} /run.py"
invoked from within
"set output [exec python $ ::env ( NF _ DESIGN _ DIR ) / test / $ { test_ name} /run.py]"
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/tcl/simple_ s
ume_ switch_ sim.tcl" line 177)
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:21:21 2019...
\end { verbatim}
\end { tiny}
Missing axi files don't abort the compilation process: (shortened for formatting)
\begin { tiny} \begin { verbatim}
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ stim.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ expected.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 1_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 1_ stim.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 1_ expected.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 2_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 2_ stim.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 2_ expected.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 3_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 3_ stim.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 3_ expected.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/dma_ 0_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/dma_ 0_ expected.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/reg_ stim.log': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/reg_ expect.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/reg_ stim.axi': No such file or directory
=== Running test /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default
... using cmd
['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py',
'--sim', 'xsim']
\end { verbatim}
\end { tiny}
Add Wave error during compilation: (shortened for formatting)
\begin { tiny} \begin { verbatim}
# add_ wave $ nf _ sume _ sdnet _ ip / out _ src _ port
# add_ wave $ nf _ sume _ sdnet _ ip / out _ dst _ port
# set const_ reg_ ip /top_ tb/top_ sim/nf_ datapath_ 0/nf_ sume_ sdnet_ wrapper_ 1/inst/SimpleSumeSwitch_ inst/const_ reg_ rw_ 0/
# add_ wave_ divider { const reg extern signals}
# add_ wave $ const _ reg _ ip
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items:
/top_ tb/top_ sim/nf_ datapath_ 0/nf_ sume_ sdnet_ wrapper_ 1/inst/SimpleSumeSwitch_ inst/const_ reg_ rw_ 0/
ERROR: [Common 17-39] 'add_ wave' failed due to earlier errors.
while executing
"add_ wave $ const _ reg _ ip "
(file "/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/tcl/simple_ sume_ switch_ sim.tcl" line 328)
INFO: [Common 17-206] Exiting Vivado at Sat May 18 15:31:59 2019...
make: *** [Makefile:121: sim] Error 1
make: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test'
512
=== Work directory is /tmp/nico/test/simple_ sume_ switch
=== Setting up test in /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 0_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 1_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 2_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/nf_ interface_ 3_ log.axi': No such file or directory
cp: cannot stat 'simple_ sume_ switch/test/dma_ 0_ log.axi': No such file or directory
=== Running test /tmp/nico/test/simple_ sume_ switch/sim_ switch_ default ...
using cmd ['/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default/run.py', '--sim', 'xsim']
[15:31] rainbow:P4-NetFPGA%
\end { verbatim}
\end { tiny}
Compilation error failing to run ``connect\_ bd\_ intf\_ net.''
\begin { tiny} \begin { verbatim}
ERROR: [BD 41-171] The modes of the interface pins 'cfg_ interrupt'(Slave) and 'pcie3_ cfg_ interrupt'(Slave) are incompatible. They cannot be connected.
ERROR: [BD 5-3] Error: running connect_ bd_ intf_ net.
ERROR: [Common 17-39] 'connect_ bd_ intf_ net' failed due to earlier errors.
while executing
"connect_ bd_ intf_ net -intf_ net nf_ riffa_ dma_ 1_ pcie3_ cfg_ interrupt [get_ bd_ intf_ pins nf_ riffa_ dma_ 1/cfg_ interrupt] [get_ bd_ intf_ pins pcie3_ 7x_ 1/pcie3_ cf..."
(procedure "create_ hier_ cell_ dma_ sub" line 141)
invoked from within
"create_ hier_ cell_ dma_ sub [current_ bd_ instance .] dma_ sub"
(procedure "create_ root_ design" line 68)
invoked from within
"create_ root_ design """
(file "./tcl/control_ sub.tcl" line 729)
while executing
"source ./tcl/control_ sub.tcl"
(file "tcl/simple_ sume_ switch.tcl" line 89)
\end { verbatim}
\end { tiny}
Compilation aborts due to missing IP:
\begin { tiny} \begin { verbatim}
### set NF_ 10G_ INTERFACE3_ BASEADDR $ M 07 _ BASEADDR
### set NF_ 10G_ INTERFACE3_ HIGHADDR $ M 07 _ HIGHADDR
### set NF_ 10G_ INTERFACE3_ SIZEADDR $ M 07 _ SIZEADDR
### set NF_ RIFFA_ DMA_ BASEADDR $ M 08 _ BASEADDR
### set NF_ RIFFA_ DMA_ HIGHADDR $ M 08 _ HIGHADDR
### set NF_ RIFFA_ DMA_ SIZEADDR $ M 08 _ SIZEADDR
Wrote :
</home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/
hw/project/simple_ sume_ switch.srcs/sources_ 1/bd/control_ sub/control_ sub.bd>
# create_ ip -name nf_ sume_ sdnet -vendor NetFPGA -library NetFPGA -module_ name nf_ sume_ sdnet_ ip
ERROR: [Coretcl 2-1134] No IP matching VLNV 'NetFPGA:NetFPGA:nf_ sume_ sdnet:*' was found. Please check your repository configuration.
INFO: [Common 17-206] Exiting Vivado at Sat May 25 11:52:01 2019...
\end { verbatim}
\end { tiny}
Mismatch: a non-critical critical error that does not abort the compilation process
\begin { tiny} \begin { verbatim}
[SW] CAM_ EnableDevice() - done
[2420698] INFO: finished packet stimulus file
[2735572] ERROR: tuple mismatch for packet 1
expected < tuple_ out_ digest_ data, tuple_ out_ sume_ metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000001010000 >
actual < tuple_ out_ digest_ data, tuple_ out_ sume_ metadata > = < 0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000010000 >
$ finish called at time : 2735572 ps : File
"/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/nf_ sume_ sdnet_ ip/SimpleSumeSwitch/Testbench/Check.v"
Line 120
\end { verbatim}
\end { tiny}
Missing interface when testing switch\_ calc:
\begin { tiny} \begin { verbatim}
root@rainbow:~/master-thesis/netpfga/minip4/sw/hw_ test_ tool# python switch_ calc_ tester.py
SIOCSIFADDR: No such device
eth1: ERROR while getting interface flags: No such device
SIOCSIFNETMASK: No such device
tcpdump: eth1: No such device exists
(SIOCGIFHWADDR: No such device)
The HW testing tool for the switch_ calc design
type help to see all commands
testing>
\end { verbatim}
\end { tiny}
Ioctl error when adding table errors on the first NetFPGA card:
\begin { verbatim}
>> table_ cam_ add_ entry lookup_ table send_ to_ port1 ff:ff:ff:ff:ff:ff =>
CAM_ Init_ ValidateContext() - done
WROTE 0x44020050 = 0xffffffff
WROTE 0x44020054 = 0xffff
WROTE 0x44020080 = 0x0003
python: ioctl: Unknown error 512
[20:27] rainbow:CLI%
\end { verbatim}
Exec format errors when loading the kernel module due to incompabilities:
\begin { tiny} \begin { verbatim}
[7:05] rainbow:netpfga% bash build-load-drivers.sh
+ cd /home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0
+ make all
make -C /lib/modules/5.0.0-16-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0 modules
make[1]: Entering directory '/usr/src/linux-headers-5.0.0-16-generic'
Building modules, stage 2.
MODPOST 1 modules
make[1]: Leaving directory '/usr/src/linux-headers-5.0.0-16-generic'
+ sudo make install
make -C /lib/modules/5.0.0-16-generic/build M=/home/nico/projects/P4-NetFPGA/lib/sw/std/driver/sume_ riffa_ v1_ 0_ 0 modules
make[1]: Entering directory '/usr/src/linux-headers-5.0.0-16-generic'
Building modules, stage 2.
MODPOST 1 modules
make[1]: Leaving directory '/usr/src/linux-headers-5.0.0-16-generic'
install -o root -g root -m 0755 -d /lib/modules/5.0.0-16-generic/extra/sume_ riffa/
install -o root -g root -m 0755 sume_ riffa.ko /lib/modules/5.0.0-16-generic/extra/sume_ riffa/
depmod -a 5.0.0-16-generic
+ sudo modprobe sume_ riffa
modprobe: ERROR: could not insert 'sume_ riffa': Exec format error
[7:06] rainbow:netpfga%
\end { verbatim}
\end { tiny}
Java traceback when trying to install SDNET:
(reason was a hidden window)
\begin { tiny}
\begin { verbatim}
Exception in thread "AWT-EventQueue-0" java.lang.IllegalArgumentException: Window must not be zero
at java.desktop/sun.awt.X11.XAtom.checkWindow(Unknown Source)
at java.desktop/sun.awt.X11.XAtom.getAtomData(Unknown Source)
at java.desktop/sun.awt.X11.XToolkit.getWorkArea(Unknown Source)
at java.desktop/sun.awt.X11.XToolkit.getInsets(Unknown Source)
at java.desktop/sun.awt.X11.XToolkit.getScreenInsets(Unknown Source)
at java.desktop/java.awt.Window.init(Unknown Source)
at java.desktop/java.awt.Window.<init>(Unknown Source)
at java.desktop/java.awt.Window.<init>(Unknown Source)
at java.desktop/java.awt.Dialog.<init>(Unknown Source)
at java.desktop/java.awt.Dialog.<init>(Unknown Source)
at java.desktop/javax.swing.JDialog.<init>(Unknown Source)
at java.desktop/javax.swing.JOptionPane.createDialog(Unknown Source)
at java.desktop/javax.swing.JOptionPane.createDialog(Unknown Source)
at j.a.c(Unknown Source)
at j.a.a(Unknown Source)
at j.a.a(Unknown Source)
at j.a.c(Unknown Source)
at com.xilinx.installer.gui.panel.destination.b.a(Unknown Source)
at com.xilinx.installer.gui.panel.destination.DestinationPanel.z(Unknown Source)
at com.xilinx.installer.gui.E.a(Unknown Source)
at com.xilinx.installer.gui.InstallerGUI.l(Unknown Source)
at com.xilinx.installer.gui.i.actionPerformed(Unknown Source)
at java.desktop/javax.swing.AbstractButton.fireActionPerformed(Unknown Source)
at java.desktop/javax.swing.AbstractButton$ Handler.actionPerformed ( Unknown Source )
at java.desktop/javax.swing.DefaultButtonModel.fireActionPerformed(Unknown Source)
at java.desktop/javax.swing.DefaultButtonModel.setPressed(Unknown Source)
at java.desktop/javax.swing.plaf.basic.BasicButtonListener.mouseReleased(Unknown Source)
at java.desktop/java.awt.Component.processMouseEvent(Unknown Source)
at java.desktop/javax.swing.JComponent.processMouseEvent(Unknown Source)
at java.desktop/java.awt.Component.processEvent(Unknown Source)
at java.desktop/java.awt.Container.processEvent(Unknown Source)
at java.desktop/java.awt.Component.dispatchEventImpl(Unknown Source)
at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source)
at java.desktop/java.awt.Component.dispatchEvent(Unknown Source)
at java.desktop/java.awt.LightweightDispatcher.retargetMouseEvent(Unknown Source)
at java.desktop/java.awt.LightweightDispatcher.processMouseEvent(Unknown Source)
at java.desktop/java.awt.LightweightDispatcher.dispatchEvent(Unknown Source)
at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source)
at java.desktop/java.awt.Window.dispatchEventImpl(Unknown Source)
at java.desktop/java.awt.Component.dispatchEvent(Unknown Source)
at java.desktop/java.awt.EventQueue.dispatchEventImpl(Unknown Source)
at java.desktop/java.awt.EventQueue.access$ 500 ( Unknown Source )
at java.desktop/java.awt.EventQueue$ 3 .run ( Unknown Source )
at java.desktop/java.awt.EventQueue$ 3 .run ( Unknown Source )
at java.base/java.security.AccessController.doPrivileged(Native Method)
at java.base/java.security.ProtectionDomain$ JavaSecurityAccessImpl.doIntersectionPrivilege ( Unknown Source )
at java.base/java.security.ProtectionDomain$ JavaSecurityAccessImpl.doIntersectionPrivilege ( Unknown Source )
at java.desktop/java.awt.EventQueue$ 4 .run ( Unknown Source )
at java.desktop/java.awt.EventQueue$ 4 .run ( Unknown Source )
at java.base/java.security.AccessController.doPrivileged(Native Method)
at java.base/java.security.ProtectionDomain$ JavaSecurityAccessImpl.doIntersectionPrivilege ( Unknown Source )
at java.desktop/java.awt.EventQueue.dispatchEvent(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.pumpOneEventForFilters(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.pumpEventsForHierarchy(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source)
at java.desktop/java.awt.EventDispatchThread.run(Unknown Source)
\end { verbatim}
\end { tiny}
Failures when testing the first NetFPGA card
\begin { tiny} \begin { verbatim}
---------------------------------------------
[ddr3B]: Running Auto Test
---------------------------------------------
Traceback (most recent call last):
File "/usr/lib/python2.7/dist-packages/wx-3.0-gtk2/wx/_ core.py", line 16765, in <lambda>
lambda event: event.callable(*event.args, **event.kw) )
File "sw/host/script/NfSumeTest.py", line 848, in UpdateProgress
self.progressDlg.Update(self.curProgress, str(localLine))
File "/usr/lib/python2.7/dist-packages/wx-3.0-gtk2/wx/_ core.py", line 16710, in _ _ getattr_ _
raise PyDeadObjectError(self.attrStr % self._name)
wx._ core.PyDeadObjectError: The C++ part of the NfSumeProgress object has been deleted, attribute access no longer allowed.
Exception in thread Thread-18:
Traceback (most recent call last):
File "/usr/lib/python2.7/threading.py", line 801, in _ _ bootstrap_ inner
self.run()
File "sw/host/script/NfSumeTest.py", line 947, in run
self.target(*self.data)
File "sw/host/script/NfSumeTest.py", line 355, in StartAutoTest
self.TestInterface(testName)
File "sw/host/script/NfSumeTest.py", line 465, in TestInterface
self.ProgramFpga('../../../bitfiles/' + self.nfSumeTestConfiguration[testName]['bitstream'])
File "sw/host/script/NfSumeTest.py", line 586, in ProgramFpga
self.getFpgaIndex()
File "sw/host/script/NfSumeTest.py", line 574, in getFpgaIndex
p = Popen(['djtgcfg', 'init', '-d', 'NetSUME'], stdout=PIPE, bufsize = 1)
File "/usr/lib/python2.7/subprocess.py", line 711, in _ _ init_ _
errread, errwrite)
File "/usr/lib/python2.7/subprocess.py", line 1343, in _ execute_ child
raise child_ exception
OSError: [Errno 2] No such file or directory
\end { verbatim}
\end { tiny}
More failures when testing the first NetFPGA card
\begin { tiny}
\begin { verbatim}
---------------------------------------------
[pcie]: Running Auto Test
---------------------------------------------
Traceback (most recent call last):
File "/usr/lib/python2.7/dist-packages/wx-3.0-gtk2/wx/_ core.py", line 16765, in <lambda>
lambda event: event.callable(*event.args, **event.kw) )
File "sw/host/script/NfSumeTest.py", line 848, in UpdateProgress
self.progressDlg.Update(self.curProgress, str(localLine))
File "/usr/lib/python2.7/dist-packages/wx-3.0-gtk2/wx/_ core.py", line 16710, in _ _ getattr_ _
raise PyDeadObjectError(self.attrStr % self._name)
wx._ core.PyDeadObjectError: The C++ part of the NfSumeProgress object has been deleted, attribute access no longer allowed.
Exception in thread Thread-21:
Traceback (most recent call last):
File "/usr/lib/python2.7/threading.py", line 801, in _ _ bootstrap_ inner
self.run()
File "sw/host/script/NfSumeTest.py", line 947, in run
self.target(*self.data)
File "sw/host/script/NfSumeTest.py", line 466, in TestInterface
self.serialCon.readlines()
File "/usr/lib/python2.7/dist-packages/serial/serialposix.py", line 495, in read
raise SerialException('device reports readiness to read but returned no data (device disconnected or multiple access on port?)')
SerialException: device reports readiness to read but returned no data (device disconnected or multiple access on port?)
\end { verbatim}
\end { tiny}
Unexpected EOF during compilation:
\begin { verbatim}
ERROR: [VRFC 10-1491] unexpected EOF
[/home/nico/master-thesis/netpfga/minip4/nf_ sume_ sdnet_ ip/
SimpleSumeSwitch/S_ CONTROLLERs.HDL/S_ CONTROLLER_ SimpleSumeSwitch.vp:37]
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 0_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 1_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 2_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 3_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 4_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 5_ ErrorCheck
INFO: [VRFC 10-311] analyzing module TopDeparser_ t_ EngineStage_ 6_ ErrorCheck
\end { verbatim}
The function syntax is not supported by p4/netfpga:
\begin { tiny}
\begin { verbatim}
make[1]: Entering directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
p4c-sdnet -o minip4.sdnet --sdnet_ info .sdnet_ switch_ info.dat minip4_ solution.p4
headers.p4(246):syntax error, unexpected IDENTIFIER, expecting (
bit<16> ones_ complement_ sum
^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
error: 1 errors encountered, aborting compilation
Makefile:34: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/src'
Makefile:31: recipe for target 'frontend' failed
make: *** [frontend] Error 2
nico@nsg-System:~/master-thesis/netpfga$
\end { verbatim}
\end { tiny}
The config\_ writes.py is missing due to a previous, non critical
compilation error:
\begin { tiny} \begin { verbatim}
nico@nsg-System:~/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/test/sim_ switch_ default$
cd $ NF _ DESIGN _ DIR / test / sim _ switch _ default & & make 2 > & 1 | tee ~ / master - thesis / netpfga / log / step 8 - $ (date +%F-%H%M%S)
rm -f config_ writes.py*
rm -f *.pyc
cp /home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_ writes.py ./
cp: cannot stat '/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/testdata/config_ writes.py': No such file or directory
Makefile:36: recipe for target 'all' failed
make: *** [all] Error 1
\end { verbatim}
\end { tiny}
Failed to synthesizing module errors:
\begin { tiny} \begin { verbatim}
WARNING: [Synth 8-689] width (12) of port connection 'control_ S_ AXI_ ARADDR' does not match port width (8) of module 'SimpleSumeSwitch'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/nf_ sume_ sdnet_ ip/wrapper/nf_ sume_ sdnet.v:199]
ERROR: [Synth 8-448] named port connection 'tuple_ out_ sume_ metadata_ VALID' does not exist for instance 'SimpleSumeSwitch_ inst' of module 'SimpleSumeSwitch'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/nf_ sume_ sdnet_ ip/wrapper/nf_ sume_ sdnet.v:218]
ERROR: [Synth 8-448] named port connection 'tuple_ out_ sume_ metadata_ DATA' does not exist for instance 'SimpleSumeSwitch_ inst' of module 'SimpleSumeSwitch'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/nf_ sume_ sdnet_ ip/wrapper/nf_ sume_ sdnet.v:219]
ERROR: [Synth 8-6156] failed synthesizing module 'nf_ sume_ sdnet'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/nf_ sume_ sdnet_ ip/wrapper/nf_ sume_ sdnet.v:44]
ERROR: [Synth 8-6156] failed synthesizing module 'nf_ sume_ sdnet_ ip'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/simple_ sume_ switch/hw/project/
simple_ sume_ switch.srcs/sources_ 1/ip/nf_ sume_ sdnet_ ip/synth/nf_ sume_ sdnet_ ip.v:57]
ERROR: [Synth 8-6156] failed synthesizing module 'nf_ datapath'
[/home/nico/projects/P4-NetFPGA/contrib-projects/sume-sdnet-switch/projects/minip4/
simple_ sume_ switch/hw/hdl/nf_ datapath.v:44]
